Andreas Sandberg has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/16002
Change subject: WIP: configs: Make example configs to Python 3 compliant
......................................................................
WIP: configs: Make example configs to Python 3 compliant
This change currently introduces issues for Python 2.7. Only use it if
you want to test gem5 with Python 3.
Change-Id: Idcea8482b286779fc98b4e144ca8f54069c08024
Signed-off-by: Andreas Sandberg <[email protected]>
---
M configs/common/BPConfig.py
M configs/common/Benchmarks.py
M configs/common/CacheConfig.py
M configs/common/Caches.py
M configs/common/CpuConfig.py
M configs/common/FSConfig.py
M configs/common/GPUTLBConfig.py
M configs/common/GPUTLBOptions.py
M configs/common/HMC.py
M configs/common/MemConfig.py
M configs/common/Options.py
M configs/common/PlatformConfig.py
M configs/common/SimpleOpts.py
M configs/common/Simulation.py
M configs/common/SysPaths.py
M configs/common/__init__.py
M configs/common/cores/__init__.py
M configs/common/cores/arm/HPI.py
M configs/common/cores/arm/O3_ARM_v7a.py
M configs/common/cores/arm/__init__.py
M configs/common/cores/arm/ex5_LITTLE.py
M configs/common/cores/arm/ex5_big.py
M configs/common/cpu2000.py
M configs/dist/sw.py
M configs/dram/lat_mem_rd.py
M configs/dram/low_power_sweep.py
M configs/dram/sweep.py
M configs/example/apu_se.py
M configs/example/arm/devices.py
M configs/example/arm/dist_bigLITTLE.py
M configs/example/arm/fs_bigLITTLE.py
M configs/example/arm/fs_power.py
M configs/example/arm/starter_fs.py
M configs/example/arm/starter_se.py
M configs/example/etrace_replay.py
M configs/example/fs.py
M configs/example/garnet_synth_traffic.py
M configs/example/hmc_hello.py
M configs/example/hmctest.py
M configs/example/memcheck.py
M configs/example/memtest.py
M configs/example/read_config.py
M configs/example/ruby_direct_test.py
M configs/example/ruby_gpu_random_test.py
M configs/example/ruby_mem_test.py
M configs/example/ruby_random_test.py
M configs/example/se.py
M configs/learning_gem5/part1/caches.py
M configs/learning_gem5/part1/simple.py
M configs/learning_gem5/part1/two_level.py
M configs/learning_gem5/part2/hello_goodbye.py
M configs/learning_gem5/part2/run_simple.py
M configs/learning_gem5/part2/simple_cache.py
M configs/learning_gem5/part2/simple_memobj.py
M configs/learning_gem5/part3/msi_caches.py
M configs/learning_gem5/part3/ruby_caches_MI_example.py
M configs/learning_gem5/part3/ruby_test.py
M configs/learning_gem5/part3/simple_ruby.py
M configs/learning_gem5/part3/test_caches.py
M configs/network/Network.py
M configs/network/__init__.py
M configs/ruby/AMD_Base_Constructor.py
M configs/ruby/GPU_RfO.py
M configs/ruby/GPU_VIPER.py
M configs/ruby/GPU_VIPER_Baseline.py
M configs/ruby/GPU_VIPER_Region.py
M configs/ruby/Garnet_standalone.py
M configs/ruby/MESI_Three_Level.py
M configs/ruby/MESI_Two_Level.py
M configs/ruby/MI_example.py
M configs/ruby/MOESI_AMD_Base.py
M configs/ruby/MOESI_CMP_directory.py
M configs/ruby/MOESI_CMP_token.py
M configs/ruby/MOESI_hammer.py
M configs/ruby/Ruby.py
M configs/splash2/cluster.py
M configs/splash2/run.py
M configs/topologies/BaseTopology.py
M configs/topologies/Cluster.py
M configs/topologies/Crossbar.py
M configs/topologies/CrossbarGarnet.py
M configs/topologies/MeshDirCorners_XY.py
M configs/topologies/Mesh_XY.py
M configs/topologies/Mesh_westfirst.py
M configs/topologies/Pt2Pt.py
M configs/topologies/__init__.py
86 files changed, 349 insertions(+), 196 deletions(-)
diff --git a/configs/common/BPConfig.py b/configs/common/BPConfig.py
index 5e5b92f..65e6d65 100644
--- a/configs/common/BPConfig.py
+++ b/configs/common/BPConfig.py
@@ -30,6 +30,7 @@
# hanle branch predictors instead of memory controllers / CPUs
from __future__ import print_function
+from __future__ import absolute_import
from m5 import fatal
import m5.objects
@@ -79,7 +80,7 @@
def bp_names():
"""Return a list of valid Branch Predictor names."""
- return _bp_classes.keys()
+ return list(_bp_classes.keys())
# Add all BPs in the object hierarchy.
for name, cls in inspect.getmembers(m5.objects, is_bp_class):
diff --git a/configs/common/Benchmarks.py b/configs/common/Benchmarks.py
index b7d10b5..3cf963b 100644
--- a/configs/common/Benchmarks.py
+++ b/configs/common/Benchmarks.py
@@ -27,8 +27,9 @@
# Authors: Ali Saidi
from __future__ import print_function
+from __future__ import absolute_import
-from SysPaths import script, disk, binary
+from .SysPaths import script, disk, binary
from os import environ as env
from m5.defines import buildEnv
@@ -141,6 +142,6 @@
None, 'android-ics')]
}
-benchs = Benchmarks.keys()
+benchs = list(Benchmarks.keys())
benchs.sort()
DefinedBenchmarks = ", ".join(benchs)
diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py
index 3fa3676..ab9d267 100644
--- a/configs/common/CacheConfig.py
+++ b/configs/common/CacheConfig.py
@@ -42,10 +42,11 @@
#
from __future__ import print_function
+from __future__ import absolute_import
import m5
from m5.objects import *
-from Caches import *
+from .Caches import *
def config_cache(options, system):
if options.external_memory_system and (options.caches or
options.l2cache):
@@ -57,13 +58,14 @@
if options.cpu_type == "O3_ARM_v7a_3":
try:
- from cores.arm.O3_ARM_v7a import *
+ import cores.arm.O3_ARM_v7a as core
except:
print("O3_ARM_v7a_3 is unavailable. Did you compile the O3
model?")
sys.exit(1)
dcache_class, icache_class, l2_cache_class, walk_cache_class = \
- O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, O3_ARM_v7aL2, \
+ core.O3_ARM_v7a_DCache, core.O3_ARM_v7a_ICache, \
+ core.O3_ARM_v7aL2, \
O3_ARM_v7aWalkCache
else:
dcache_class, icache_class, l2_cache_class, walk_cache_class = \
@@ -97,7 +99,7 @@
if options.memchecker:
system.memchecker = MemChecker()
- for i in xrange(options.num_cpus):
+ for i in range(options.num_cpus):
if options.caches:
icache = icache_class(size=options.l1i_size,
assoc=options.l1i_assoc)
diff --git a/configs/common/Caches.py b/configs/common/Caches.py
index 926a41d..f8edc8b 100644
--- a/configs/common/Caches.py
+++ b/configs/common/Caches.py
@@ -38,6 +38,9 @@
#
# Authors: Lisa Hsu
+from __future__ import print_function
+from __future__ import absolute_import
+
from m5.defines import buildEnv
from m5.objects import *
diff --git a/configs/common/CpuConfig.py b/configs/common/CpuConfig.py
index f0d009e..35d1036 100644
--- a/configs/common/CpuConfig.py
+++ b/configs/common/CpuConfig.py
@@ -36,6 +36,7 @@
# Authors: Andreas Sandberg
from __future__ import print_function
+from __future__ import absolute_import
from m5 import fatal
import m5.objects
@@ -98,7 +99,7 @@
def cpu_names():
"""Return a list of valid CPU names."""
- return _cpu_classes.keys()
+ return list(_cpu_classes.keys())
def config_etrace(cpu_cls, cpu_list, options):
if issubclass(cpu_cls, m5.objects.DerivO3CPU):
diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index 04793e9..73e965e 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -40,11 +40,12 @@
# Authors: Kevin Lim
from __future__ import print_function
+from __future__ import absolute_import
from m5.objects import *
-from Benchmarks import *
from m5.util import *
-from common import PlatformConfig
+from .Benchmarks import *
+from . import PlatformConfig
# Populate to reflect supported os types per target ISA
os_types = { 'alpha' : [ 'linux' ],
@@ -548,7 +549,7 @@
# Set up the Intel MP table
base_entries = []
ext_entries = []
- for i in xrange(numCPUs):
+ for i in range(numCPUs):
bp = X86IntelMPProcessor(
local_apic_id = i,
local_apic_version = 0x14,
diff --git a/configs/common/GPUTLBConfig.py b/configs/common/GPUTLBConfig.py
index 3e47f1d..d93b68e 100644
--- a/configs/common/GPUTLBConfig.py
+++ b/configs/common/GPUTLBConfig.py
@@ -32,6 +32,7 @@
# Authors: Lisa Hsu
from __future__ import print_function
+from __future__ import absolute_import
# Configure the TLB hierarchy
# Places which would probably need to be modified if you
@@ -69,7 +70,7 @@
def create_TLB_Coalescer(options, my_level, my_index, TLB_name,
Coalescer_name):
# arguments: options, TLB level, number of private structures for this
Level,
# TLB name and Coalescer name
- for i in xrange(my_index):
+ for i in range(my_index):
TLB_name.append(eval(TLB_constructor(my_level)))
Coalescer_name.append(eval(Coalescer_constructor(my_level)))
@@ -109,7 +110,7 @@
# Create the hiearchy
# Call the appropriate constructors and add objects to the system
- for i in xrange(len(TLB_hierarchy)):
+ for i in range(len(TLB_hierarchy)):
hierarchy_level = TLB_hierarchy[i]
level = i+1
for TLB_type in hierarchy_level:
@@ -143,7 +144,7 @@
# Each TLB is connected with its Coalescer through a single port.
# There is a one-to-one mapping of TLBs to Coalescers at a given level
# This won't be modified no matter what the hierarchy looks like.
- for i in xrange(len(TLB_hierarchy)):
+ for i in range(len(TLB_hierarchy)):
hierarchy_level = TLB_hierarchy[i]
level = i+1
for TLB_type in hierarchy_level:
@@ -159,7 +160,7 @@
name = TLB_type['name']
num_TLBs = TLB_type['width']
if name == 'l1': # L1 D-TLBs
- tlb_per_cu = num_TLBs / n_cu
+ tlb_per_cu = num_TLBs // n_cu
for cu_idx in range(n_cu):
if tlb_per_cu:
for tlb in range(tlb_per_cu):
diff --git a/configs/common/GPUTLBOptions.py
b/configs/common/GPUTLBOptions.py
index 9e370c1..fdcec5d 100644
--- a/configs/common/GPUTLBOptions.py
+++ b/configs/common/GPUTLBOptions.py
@@ -31,6 +31,9 @@
#
# Authors: Myrto Papadopoulou
+from __future__ import print_function
+from __future__ import absolute_import
+
def tlb_options(parser):
#===================================================================
diff --git a/configs/common/HMC.py b/configs/common/HMC.py
index 10d8a71..08b217d 100644
--- a/configs/common/HMC.py
+++ b/configs/common/HMC.py
@@ -122,6 +122,9 @@
# 2 Crossbars are connected to only local vaults. From other 2 crossbar,
a
# request can be forwarded to any other vault.
+from __future__ import print_function
+from __future__ import absolute_import
+
import argparse
import m5
@@ -337,16 +340,16 @@
num_lanes=opt.num_lanes_per_link,
link_speed=opt.serial_link_speed,
delay=opt.total_ctrl_latency) for i in
- xrange(opt.num_serial_links)]
+ range(opt.num_serial_links)]
system.hmc_host.seriallink = sl
# enable global monitor
if opt.enable_global_monitor:
system.hmc_host.lmonitor = [CommMonitor() for i in
- xrange(opt.num_serial_links)]
+ range(opt.num_serial_links)]
# set the clock frequency for serial link
- for i in xrange(opt.num_serial_links):
+ for i in range(opt.num_serial_links):
clk = opt.link_controller_frequency
vd = VoltageDomain(voltage='1V')
scd = SrcClockDomain(clock=clk, voltage_domain=vd)
@@ -357,7 +360,7 @@
hh = system.hmc_host
if opt.arch == "distributed":
mb = system.membus
- for i in xrange(opt.num_links_controllers):
+ for i in range(opt.num_links_controllers):
if opt.enable_global_monitor:
mb.master = hh.lmonitor[i].slave
hh.lmonitor[i].master = hh.seriallink[i].slave
@@ -375,7 +378,7 @@
mb.master = hh.seriallink[1].slave
if opt.arch == "same":
- for i in xrange(opt.num_links_controllers):
+ for i in range(opt.num_links_controllers):
if opt.enable_global_monitor:
hh.lmonitor[i].master = hh.seriallink[i].slave
@@ -395,7 +398,7 @@
system.mem_ranges = addr_ranges_vaults
if opt.enable_link_monitor:
- lm = [CommMonitor() for i in xrange(opt.num_links_controllers)]
+ lm = [CommMonitor() for i in range(opt.num_links_controllers)]
system.hmc_dev.lmonitor = lm
# 4 HMC Crossbars located in its logic-base (LoB)
@@ -403,17 +406,17 @@
frontend_latency=opt.xbar_frontend_latency,
forward_latency=opt.xbar_forward_latency,
response_latency=opt.xbar_response_latency) for
i in
- xrange(opt.number_mem_crossbar)]
+ range(opt.number_mem_crossbar)]
system.hmc_dev.xbar = xb
- for i in xrange(opt.number_mem_crossbar):
+ for i in range(opt.number_mem_crossbar):
clk = opt.xbar_frequency
vd = VoltageDomain(voltage='1V')
scd = SrcClockDomain(clock=clk, voltage_domain=vd)
system.hmc_dev.xbar[i].clk_domain = scd
# Attach 4 serial link to 4 crossbar/s
- for i in xrange(opt.num_serial_links):
+ for i in range(opt.num_serial_links):
if opt.enable_link_monitor:
system.hmc_host.seriallink[i].master = \
system.hmc_dev.lmonitor[i].slave
@@ -429,7 +432,7 @@
# create a list of buffers
system.hmc_dev.buffers = [Bridge(req_size=opt.xbar_buffer_size_req,
resp_size=opt.xbar_buffer_size_resp)
- for i in xrange(numx*(opt.mem_chunk-1))]
+ for i in range(numx*(opt.mem_chunk-1))]
# Buffer iterator
it = iter(range(len(system.hmc_dev.buffers)))
diff --git a/configs/common/MemConfig.py b/configs/common/MemConfig.py
index 3603580..0d306a4 100644
--- a/configs/common/MemConfig.py
+++ b/configs/common/MemConfig.py
@@ -37,13 +37,21 @@
# Andreas Hansson
from __future__ import print_function
+from __future__ import absolute_import
import m5.objects
import inspect
import sys
-import HMC
from textwrap import TextWrapper
+try:
+ # Common was added to the import and someone executed import
+ # MemConfig
+ import HMC
+except ImportError:
+ # MemConfig was imported from the common package
+ from . import HMC
+
# Dictionary of mapping names of real memory controller models to
# classes.
_mem_classes = {}
@@ -86,7 +94,7 @@
def mem_names():
"""Return a list of valid memory names."""
- return _mem_classes.keys()
+ return list(_mem_classes.keys())
# Add all memory controllers in the object hierarchy.
for name, cls in inspect.getmembers(m5.objects, is_mem_class):
@@ -215,7 +223,7 @@
# array of controllers and set their parameters to match their
# address mapping in the case of a DRAM
for r in system.mem_ranges:
- for i in xrange(nbr_mem_ctrls):
+ for i in range(nbr_mem_ctrls):
mem_ctrl = create_mem_ctrl(cls, r, i, nbr_mem_ctrls,
intlv_bits,
intlv_size)
# Set the number of ranks based on the command-line
@@ -233,7 +241,7 @@
subsystem.mem_ctrls = mem_ctrls
# Connect the controllers to the membus
- for i in xrange(len(subsystem.mem_ctrls)):
+ for i in range(len(subsystem.mem_ctrls)):
if opt_mem_type == "HMC_2500_1x32":
subsystem.mem_ctrls[i].port = xbar[i/4].master
# Set memory device size. There is an independent controller
for
diff --git a/configs/common/Options.py b/configs/common/Options.py
index 7963013..9e76899 100644
--- a/configs/common/Options.py
+++ b/configs/common/Options.py
@@ -38,6 +38,9 @@
#
# Authors: Lisa Hsu
+from __future__ import print_function
+from __future__ import absolute_import
+
import m5
from m5.defines import buildEnv
from m5.objects import *
@@ -330,7 +333,7 @@
help="Redirect stderr to a file.")
def addFSOptions(parser):
- from FSConfig import os_types
+ from .FSConfig import os_types
# Simulation options
parser.add_option("--timesync", action="store_true",
@@ -339,8 +342,9 @@
# System options
parser.add_option("--kernel", action="store", type="string")
parser.add_option("--os-type", action="store", type="choice",
- choices=os_types[buildEnv['TARGET_ISA']], default="linux",
- help="Specifies type of OS to boot")
+ choices=os_types[str(buildEnv['TARGET_ISA'])],
+ default="linux",
+ help="Specifies type of OS to boot")
parser.add_option("--script", action="store", type="string")
parser.add_option("--frame-capture", action="store_true",
help="Stores changed frame buffers from the VNC server to
compressed "\
diff --git a/configs/common/PlatformConfig.py
b/configs/common/PlatformConfig.py
index 306b732..0c2ef36 100644
--- a/configs/common/PlatformConfig.py
+++ b/configs/common/PlatformConfig.py
@@ -39,6 +39,7 @@
# Pierre-Yves Peneau
from __future__ import print_function
+from __future__ import absolute_import
import m5.objects
import inspect
@@ -103,7 +104,7 @@
def platform_names():
"""Return a list of valid Platform names."""
- return _platform_classes.keys() + _platform_aliases.keys()
+ return list(_platform_classes.keys()) + list(_platform_aliases.keys())
# Add all Platforms in the object hierarchy.
for name, cls in inspect.getmembers(m5.objects, is_platform_class):
diff --git a/configs/common/SimpleOpts.py b/configs/common/SimpleOpts.py
index e2f122e..32e3447 100644
--- a/configs/common/SimpleOpts.py
+++ b/configs/common/SimpleOpts.py
@@ -27,6 +27,9 @@
#
# Authors: Jason Power
+from __future__ import print_function
+from __future__ import absolute_import
+
""" Options wrapper for simple gem5 configuration scripts
This module wraps the optparse class so that we can register options
diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py
index 19bd962..5eefde9 100644
--- a/configs/common/Simulation.py
+++ b/configs/common/Simulation.py
@@ -40,6 +40,7 @@
# Authors: Lisa Hsu
from __future__ import print_function
+from __future__ import absolute_import
import sys
from os import getcwd
@@ -453,18 +454,18 @@
switch_cpus = None
if options.prog_interval:
- for i in xrange(np):
+ for i in range(np):
testsys.cpu[i].progress_interval = options.prog_interval
if options.maxinsts:
- for i in xrange(np):
+ for i in range(np):
testsys.cpu[i].max_insts_any_thread = options.maxinsts
if cpu_class:
switch_cpus = [cpu_class(switched_out=True, cpu_id=(i))
- for i in xrange(np)]
+ for i in range(np)]
- for i in xrange(np):
+ for i in range(np):
if options.fast_forward:
testsys.cpu[i].max_insts_any_thread =
int(options.fast_forward)
switch_cpus[i].system = testsys
@@ -489,7 +490,7 @@
CpuConfig.config_etrace(cpu_class, switch_cpus, options)
testsys.switch_cpus = switch_cpus
- switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in
xrange(np)]
+ switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in
range(np)]
if options.repeat_switch:
switch_class = getCPUClass(options.cpu_type)[0]
@@ -502,9 +503,9 @@
sys.exit(1)
repeat_switch_cpus = [switch_class(switched_out=True, \
- cpu_id=(i)) for i in
xrange(np)]
+ cpu_id=(i)) for i in
range(np)]
- for i in xrange(np):
+ for i in range(np):
repeat_switch_cpus[i].system = testsys
repeat_switch_cpus[i].workload = testsys.cpu[i].workload
repeat_switch_cpus[i].clk_domain = testsys.cpu[i].clk_domain
@@ -520,18 +521,18 @@
if cpu_class:
repeat_switch_cpu_list = [(switch_cpus[i],
repeat_switch_cpus[i])
- for i in xrange(np)]
+ for i in range(np)]
else:
repeat_switch_cpu_list = [(testsys.cpu[i],
repeat_switch_cpus[i])
- for i in xrange(np)]
+ for i in range(np)]
if options.standard_switch:
switch_cpus = [TimingSimpleCPU(switched_out=True, cpu_id=(i))
- for i in xrange(np)]
+ for i in range(np)]
switch_cpus_1 = [DerivO3CPU(switched_out=True, cpu_id=(i))
- for i in xrange(np)]
+ for i in range(np)]
- for i in xrange(np):
+ for i in range(np):
switch_cpus[i].system = testsys
switch_cpus_1[i].system = testsys
switch_cpus[i].workload = testsys.cpu[i].workload
@@ -572,8 +573,12 @@
testsys.switch_cpus = switch_cpus
testsys.switch_cpus_1 = switch_cpus_1
- switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in
xrange(np)]
- switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in
xrange(np)]
+ switch_cpu_list = [
+ (testsys.cpu[i], switch_cpus[i]) for i in range(np)
+ ]
+ switch_cpu_list1 = [
+ (switch_cpus[i], switch_cpus_1[i]) for i in range(np)
+ ]
# set the checkpoint in the cpu before m5.instantiate is called
if options.take_checkpoints != None and \
@@ -581,7 +586,7 @@
offset = int(options.take_checkpoints)
# Set an instruction break point
if options.simpoint:
- for i in xrange(np):
+ for i in range(np):
if testsys.cpu[i].workload[0].simpoint == 0:
fatal('no simpoint for testsys.cpu[%d].workload[0]', i)
checkpoint_inst = int(testsys.cpu[i].workload[0].simpoint)
+ offset
@@ -592,7 +597,7 @@
options.take_checkpoints = offset
# Set all test cpus with the right number of instructions
# for the upcoming simulation
- for i in xrange(np):
+ for i in range(np):
testsys.cpu[i].max_insts_any_thread = offset
if options.take_simpoint_checkpoints != None:
diff --git a/configs/common/SysPaths.py b/configs/common/SysPaths.py
index 9a234cc..e5d9f83 100644
--- a/configs/common/SysPaths.py
+++ b/configs/common/SysPaths.py
@@ -26,6 +26,10 @@
#
# Authors: Ali Saidi
+from __future__ import print_function
+from __future__ import absolute_import
+
+from six import string_types
import os, sys
config_path = os.path.dirname(os.path.abspath(__file__))
@@ -35,7 +39,7 @@
_sys_paths = None
def __init__(self, subdirs, sys_paths=None):
- if isinstance(subdirs, basestring):
+ if isinstance(subdirs, string_types):
subdirs = [subdirs]
self._subdir = os.path.join(*subdirs)
if sys_paths:
@@ -55,16 +59,16 @@
paths = filter(os.path.isdir, paths)
if not paths:
- raise IOError, "Can't find a path to system files."
+ raise IOError("Can't find a path to system files.")
- self._sys_paths = paths
+ self._sys_paths = list(paths)
filepath = os.path.join(self._subdir, filename)
paths = (os.path.join(p, filepath) for p in self._sys_paths)
try:
return next(p for p in paths if os.path.exists(p))
except StopIteration:
- raise IOError, "Can't find file '%s' on path." % filename
+ raise IOError("Can't find file '%s' on path." % filename)
disk = PathSearchFunc('disks')
binary = PathSearchFunc('binaries')
diff --git a/configs/common/__init__.py b/configs/common/__init__.py
index 1829385..5e72a60 100644
--- a/configs/common/__init__.py
+++ b/configs/common/__init__.py
@@ -34,3 +34,7 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Andreas Hansson
+
+from __future__ import print_function
+from __future__ import absolute_import
+
diff --git a/configs/common/cores/__init__.py
b/configs/common/cores/__init__.py
index 7a2173e..c61e6d8 100644
--- a/configs/common/cores/__init__.py
+++ b/configs/common/cores/__init__.py
@@ -34,3 +34,6 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Andreas Sandberg
+
+from __future__ import print_function
+from __future__ import absolute_import
diff --git a/configs/common/cores/arm/HPI.py
b/configs/common/cores/arm/HPI.py
index 2efb7df..01c0884 100644
--- a/configs/common/cores/arm/HPI.py
+++ b/configs/common/cores/arm/HPI.py
@@ -46,6 +46,7 @@
"""
from __future__ import print_function
+from __future__ import absolute_import
from m5.objects import *
@@ -177,7 +178,7 @@
defns = []
# Then apply them to the produced new env
- for i in xrange(0, len(bindings)):
+ for i in range(0, len(bindings)):
name, binding_expr = bindings[i]
defns.append(binding_expr(new_env))
diff --git a/configs/common/cores/arm/O3_ARM_v7a.py
b/configs/common/cores/arm/O3_ARM_v7a.py
index b0ba128..3a1f9af 100644
--- a/configs/common/cores/arm/O3_ARM_v7a.py
+++ b/configs/common/cores/arm/O3_ARM_v7a.py
@@ -26,6 +26,8 @@
#
# Authors: Ron Dreslinski
+from __future__ import print_function
+from __future__ import absolute_import
from m5.objects import *
diff --git a/configs/common/cores/arm/__init__.py
b/configs/common/cores/arm/__init__.py
index 582e6b8..45b11a3 100644
--- a/configs/common/cores/arm/__init__.py
+++ b/configs/common/cores/arm/__init__.py
@@ -35,6 +35,9 @@
#
# Authors: Andreas Sandberg
+from __future__ import print_function
+from __future__ import absolute_import
+
from pkgutil import iter_modules
from importlib import import_module
diff --git a/configs/common/cores/arm/ex5_LITTLE.py
b/configs/common/cores/arm/ex5_LITTLE.py
index 1ae0f16..85fdd55 100644
--- a/configs/common/cores/arm/ex5_LITTLE.py
+++ b/configs/common/cores/arm/ex5_LITTLE.py
@@ -29,6 +29,9 @@
# Anastasiia Butko
# Louisa Bessad
+from __future__ import print_function
+from __future__ import absolute_import
+
from m5.objects import *
#-----------------------------------------------------------------------
diff --git a/configs/common/cores/arm/ex5_big.py
b/configs/common/cores/arm/ex5_big.py
index 96323f4..445aa32 100644
--- a/configs/common/cores/arm/ex5_big.py
+++ b/configs/common/cores/arm/ex5_big.py
@@ -29,6 +29,9 @@
# Anastasiia Butko
# Louisa Bessad
+from __future__ import print_function
+from __future__ import absolute_import
+
from m5.objects import *
#-----------------------------------------------------------------------
diff --git a/configs/common/cpu2000.py b/configs/common/cpu2000.py
index da87507..730a478 100644
--- a/configs/common/cpu2000.py
+++ b/configs/common/cpu2000.py
@@ -27,6 +27,7 @@
# Authors: Nathan Binkert
from __future__ import print_function
+from __future__ import absolute_import
import os
import sys
@@ -93,13 +94,13 @@
try:
func = getattr(self.__class__, input_set)
except AttributeError:
- raise AttributeError, \
- 'The benchmark %s does not have the %s input set' % \
- (self.name, input_set)
+ raise AttributeError(
+ 'The benchmark %s does not have the %s input set' % \
+ (self.name, input_set))
executable = joinpath(spec_dist, 'binaries', isa, os, self.binary)
if not isfile(executable):
- raise AttributeError, '%s not found' % executable
+ raise AttributeError('%s not found' % executable)
self.executable = executable
# root of tree for input & output data files
@@ -113,7 +114,7 @@
self.input_set = input_set
if not isdir(inputs_dir):
- raise AttributeError, '%s not found' % inputs_dir
+ raise AttributeError('%s not found' % inputs_dir)
self.inputs_dir = [ inputs_dir ]
if isdir(all_dir):
@@ -670,7 +671,7 @@
elif (isa == 'sparc' or isa == 'sparc32'):
self.endian = 'bendian'
else:
- raise AttributeError, "unknown ISA %s" % isa
+ raise AttributeError("unknown ISA %s" % isa)
super(vortex, self).__init__(isa, os, input_set)
diff --git a/configs/dist/sw.py b/configs/dist/sw.py
index e7f31c0..8dca62f 100644
--- a/configs/dist/sw.py
+++ b/configs/dist/sw.py
@@ -57,7 +57,7 @@
sync_repeat =
options.dist_sync_repeat,
is_switch = True,
num_nodes = options.dist_size)
- for i in xrange(options.dist_size)]
+ for i in range(options.dist_size)]
for (i, link) in enumerate(switch.portlink):
link.int0 = switch.interface[i]
diff --git a/configs/dram/lat_mem_rd.py b/configs/dram/lat_mem_rd.py
index dc80bd2..fd92a63 100644
--- a/configs/dram/lat_mem_rd.py
+++ b/configs/dram/lat_mem_rd.py
@@ -36,6 +36,7 @@
# Authors: Andreas Hansson
from __future__ import print_function
+from __future__ import absolute_import
import gzip
import optparse
@@ -188,7 +189,7 @@
protolib.encodeMessage(proto_out, header)
# create a list of every single address to touch
- addrs = range(0, max_addr, burst_size)
+ addrs = list(range(0, max_addr, burst_size))
import random
random.shuffle(addrs)
diff --git a/configs/dram/low_power_sweep.py
b/configs/dram/low_power_sweep.py
index 2aa6490..6b4313b 100644
--- a/configs/dram/low_power_sweep.py
+++ b/configs/dram/low_power_sweep.py
@@ -37,6 +37,7 @@
# Andreas Hansson
from __future__ import print_function
+from __future__ import absolute_import
import argparse
@@ -166,11 +167,11 @@
# We sweep itt max using the multipliers specified by the user.
itt_max_str = args.itt_list.strip().split()
-itt_max_multiples = map(lambda x : int(x), itt_max_str)
+itt_max_multiples = [ int(x) for x in itt_max_str ]
if len(itt_max_multiples) == 0:
fatal("String for itt-max-list detected empty\n")
-itt_max_values = map(lambda m : pd_entry_time * m, itt_max_multiples)
+itt_max_values = [ pd_entry_time * m for m in itt_max_multiples ]
# Generate request addresses in the entire range, assume we start at 0
max_addr = mem_range.end
diff --git a/configs/dram/sweep.py b/configs/dram/sweep.py
index 10ef748..61b3164 100644
--- a/configs/dram/sweep.py
+++ b/configs/dram/sweep.py
@@ -36,6 +36,7 @@
# Authors: Andreas Hansson
from __future__ import print_function
+from __future__ import absolute_import
import math
import optparse
diff --git a/configs/example/apu_se.py b/configs/example/apu_se.py
index bba0d0f..2b2d9c8 100644
--- a/configs/example/apu_se.py
+++ b/configs/example/apu_se.py
@@ -32,6 +32,7 @@
# Authors: Sooraj Puthoor
from __future__ import print_function
+from __future__ import absolute_import
import optparse, os, re
import math
@@ -225,7 +226,7 @@
# List of compute units; one GPU can have multiple compute units
compute_units = []
-for i in xrange(n_cu):
+for i in range(n_cu):
compute_units.append(ComputeUnit(cu_id = i, perLaneTLB = per_lane,
num_SIMDs = options.simds_per_cu,
wfSize = options.wf_size,
@@ -255,8 +256,8 @@
options.outOfOrderDataDelivery))
wavefronts = []
vrfs = []
- for j in xrange(options.simds_per_cu):
- for k in xrange(shader.n_wf):
+ for j in range(options.simds_per_cu):
+ for k in range(shader.n_wf):
wavefronts.append(Wavefront(simdId = j, wf_slot_id = k,
wfSize = options.wf_size))
vrfs.append(VectorRegisterFile(simd_id=j,
@@ -311,7 +312,7 @@
future_cpu_list = []
# Initial CPUs to be used during fast-forwarding.
- for i in xrange(options.num_cpus):
+ for i in range(options.num_cpus):
cpu = CpuClass(cpu_id = i,
clk_domain = SrcClockDomain(
clock = options.CPUClock,
@@ -328,7 +329,7 @@
MainCpuClass = CpuClass
# CPs to be used throughout the simulation.
-for i in xrange(options.num_cp):
+for i in range(options.num_cp):
cp = MainCpuClass(cpu_id = options.num_cpus + i,
clk_domain = SrcClockDomain(
clock = options.CPUClock,
@@ -337,7 +338,7 @@
cp_list.append(cp)
# Main CPUs (to be used after fast-forwarding if fast-forwarding is
specified).
-for i in xrange(options.num_cpus):
+for i in range(options.num_cpus):
cpu = MainCpuClass(cpu_id = i,
clk_domain = SrcClockDomain(
clock = options.CPUClock,
@@ -400,7 +401,7 @@
cp.workload = host_cpu.workload
if fast_forward:
- for i in xrange(len(future_cpu_list)):
+ for i in range(len(future_cpu_list)):
future_cpu_list[i].workload = cpu_list[i].workload
future_cpu_list[i].createThreads()
@@ -408,7 +409,7 @@
# List of CPUs that must be switched when moving between KVM and simulation
if fast_forward:
switch_cpu_list = \
- [(cpu_list[i], future_cpu_list[i]) for i in
xrange(options.num_cpus)]
+ [(cpu_list[i], future_cpu_list[i]) for i in
range(options.num_cpus)]
# Full list of processing cores in the system. Note that
# dispatcher is also added to cpu_list although it is
@@ -431,7 +432,7 @@
have_kvm_support = 'BaseKvmCPU' in globals()
if have_kvm_support and buildEnv['TARGET_ISA'] == "x86":
system.vm = KvmVM()
- for i in xrange(len(host_cpu.workload)):
+ for i in range(len(host_cpu.workload)):
host_cpu.workload[i].useArchPT = True
host_cpu.workload[i].kvmInSE = True
else:
@@ -479,15 +480,15 @@
gpu_port_idx = gpu_port_idx - options.num_cp * 2
wavefront_size = options.wf_size
-for i in xrange(n_cu):
+for i in range(n_cu):
# The pipeline issues wavefront_size number of uncoalesced requests
# in one GPU issue cycle. Hence wavefront_size mem ports.
- for j in xrange(wavefront_size):
+ for j in range(wavefront_size):
system.cpu[shader_idx].CUs[i].memory_port[j] = \
system.ruby._cpu_ports[gpu_port_idx].slave[j]
gpu_port_idx += 1
-for i in xrange(n_cu):
+for i in range(n_cu):
if i > 0 and not i % options.cu_per_sqc:
print("incrementing idx on ", i)
gpu_port_idx += 1
@@ -496,7 +497,7 @@
gpu_port_idx = gpu_port_idx + 1
# attach CP ports to Ruby
-for i in xrange(options.num_cp):
+for i in range(options.num_cp):
system.cpu[cp_idx].createInterruptController()
system.cpu[cp_idx].dcache_port = \
system.ruby._cpu_ports[gpu_port_idx + i * 2].slave
diff --git a/configs/example/arm/devices.py b/configs/example/arm/devices.py
index 15492cb..3f3bdfb 100644
--- a/configs/example/arm/devices.py
+++ b/configs/example/arm/devices.py
@@ -38,6 +38,9 @@
# System components used by the bigLITTLE.py configuration script
+from __future__ import print_function
+from __future__ import absolute_import
+
import m5
from m5.objects import *
m5.util.addToPath('../../')
diff --git a/configs/example/arm/dist_bigLITTLE.py
b/configs/example/arm/dist_bigLITTLE.py
index 5194fc7..5bce3fd 100644
--- a/configs/example/arm/dist_bigLITTLE.py
+++ b/configs/example/arm/dist_bigLITTLE.py
@@ -38,6 +38,9 @@
# This configuration file extends the example ARM big.LITTLE(tm)
# configuration to enabe dist-gem5 siulations of big.LITTLE systems.
+from __future__ import print_function
+from __future__ import absolute_import
+
import argparse
import os
diff --git a/configs/example/arm/fs_bigLITTLE.py
b/configs/example/arm/fs_bigLITTLE.py
index 8cf89e3..6f18b98 100644
--- a/configs/example/arm/fs_bigLITTLE.py
+++ b/configs/example/arm/fs_bigLITTLE.py
@@ -41,6 +41,7 @@
from __future__ import print_function
+from __future__ import absolute_import
import argparse
import os
diff --git a/configs/example/arm/fs_power.py
b/configs/example/arm/fs_power.py
index 7b92c8d..0de6568 100644
--- a/configs/example/arm/fs_power.py
+++ b/configs/example/arm/fs_power.py
@@ -40,6 +40,7 @@
# with example power models.
from __future__ import print_function
+from __future__ import absolute_import
import argparse
import os
diff --git a/configs/example/arm/starter_fs.py
b/configs/example/arm/starter_fs.py
index a199768..b9756ab 100644
--- a/configs/example/arm/starter_fs.py
+++ b/configs/example/arm/starter_fs.py
@@ -44,6 +44,7 @@
"""
from __future__ import print_function
+from __future__ import absolute_import
import os
import m5
diff --git a/configs/example/arm/starter_se.py
b/configs/example/arm/starter_se.py
index ef218d9..b76be5f 100644
--- a/configs/example/arm/starter_se.py
+++ b/configs/example/arm/starter_se.py
@@ -44,6 +44,7 @@
"""
from __future__ import print_function
+from __future__ import absolute_import
import os
import m5
diff --git a/configs/example/etrace_replay.py
b/configs/example/etrace_replay.py
index e64871a..588d0a4 100644
--- a/configs/example/etrace_replay.py
+++ b/configs/example/etrace_replay.py
@@ -38,6 +38,7 @@
# Basic elastic traces replay script that configures a Trace CPU
from __future__ import print_function
+from __future__ import absolute_import
import optparse
diff --git a/configs/example/fs.py b/configs/example/fs.py
index 4d21658..9992fff 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -42,6 +42,7 @@
# Brad Beckmann
from __future__ import print_function
+from __future__ import absolute_import
import optparse
import sys
@@ -138,7 +139,7 @@
# For now, assign all the CPUs to the same clock domain
test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain,
cpu_id=i)
- for i in xrange(np)]
+ for i in range(np)]
if CpuConfig.is_kvm_cpu(TestCPUClass) or
CpuConfig.is_kvm_cpu(FutureClass):
test_sys.kvm_vm = KvmVM()
@@ -194,7 +195,7 @@
if np > 1:
fatal("SimPoint generation not supported with more than
one CPUs")
- for i in xrange(np):
+ for i in range(np):
if options.simpoint_profile:
test_sys.cpu[i].addSimPointProbe(options.simpoint_interval)
if options.checker:
@@ -277,7 +278,7 @@
# memory bus
drive_sys.mem_ctrls = [DriveMemClass(range = r)
for r in drive_sys.mem_ranges]
- for i in xrange(len(drive_sys.mem_ctrls)):
+ for i in range(len(drive_sys.mem_ctrls)):
drive_sys.mem_ctrls[i].port = drive_sys.membus.master
drive_sys.init_param = options.init_param
diff --git a/configs/example/garnet_synth_traffic.py
b/configs/example/garnet_synth_traffic.py
index 92fb3a0..8396ddb 100644
--- a/configs/example/garnet_synth_traffic.py
+++ b/configs/example/garnet_synth_traffic.py
@@ -27,6 +27,7 @@
# Author: Tushar Krishna
from __future__ import print_function
+from __future__ import absolute_import
import m5
from m5.objects import *
@@ -87,7 +88,8 @@
#
Ruby.define_options(parser)
-execfile(os.path.join(config_root, "common", "Options.py"))
+exec(compile(open(os.path.join(config_root, "common", "Options.py")).read(),
+ os.path.join(config_root, "common", "Options.py"), 'exec'))
(options, args) = parser.parse_args()
@@ -112,7 +114,7 @@
inj_vnet=options.inj_vnet,
precision=options.precision,
num_dest=options.num_dirs) \
- for i in xrange(options.num_cpus) ]
+ for i in range(options.num_cpus) ]
# create the desired simulated system
system = System(cpu = cpus, mem_ranges = [AddrRange(options.mem_size)])
diff --git a/configs/example/hmc_hello.py b/configs/example/hmc_hello.py
index d9a6c0f..a682519 100644
--- a/configs/example/hmc_hello.py
+++ b/configs/example/hmc_hello.py
@@ -30,6 +30,9 @@
#
# Author: Éder F. Zulian
+from __future__ import print_function
+from __future__ import absolute_import
+
import sys
import argparse
diff --git a/configs/example/hmctest.py b/configs/example/hmctest.py
index c370d0a..32a8222 100644
--- a/configs/example/hmctest.py
+++ b/configs/example/hmctest.py
@@ -1,4 +1,6 @@
+
from __future__ import print_function
+from __future__ import absolute_import
import sys
import argparse
@@ -57,17 +59,17 @@
system.clk_domain = SrcClockDomain(clock=clk, voltage_domain=vd)
# add traffic generators to the system
system.tgen = [TrafficGen(config_file=options.tgen_cfg_file) for i in
- xrange(options.num_tgen)]
+ range(options.num_tgen)]
# Config memory system with given HMC arch
MemConfig.config_mem(options, system)
# Connect the traffic generatiors
if options.arch == "distributed":
- for i in xrange(options.num_tgen):
+ for i in range(options.num_tgen):
system.tgen[i].port = system.membus.slave
# connect the system port even if it is not used in this example
system.system_port = system.membus.slave
if options.arch == "mixed":
- for i in xrange(int(options.num_tgen/2)):
+ for i in range(int(options.num_tgen/2)):
system.tgen[i].port = system.membus.slave
hh = system.hmc_host
if options.enable_global_monitor:
@@ -82,7 +84,7 @@
system.system_port = system.membus.slave
if options.arch == "same":
hh = system.hmc_host
- for i in xrange(options.num_links_controllers):
+ for i in range(options.num_links_controllers):
if options.enable_global_monitor:
system.tgen[i].port = hh.lmonitor[i].slave
else:
diff --git a/configs/example/memcheck.py b/configs/example/memcheck.py
index c2eed19..e758b67 100644
--- a/configs/example/memcheck.py
+++ b/configs/example/memcheck.py
@@ -40,6 +40,7 @@
# Andreas Hansson
from __future__ import print_function
+from __future__ import absolute_import
import optparse
import random
@@ -246,9 +247,9 @@
# The levels are indexing backwards through the list
ntesters = testerspec[len(cachespec) - level]
- testers = [proto_tester() for i in xrange(ntesters)]
+ testers = [proto_tester() for i in range(ntesters)]
checkers = [MemCheckerMonitor(memchecker = system.memchecker) \
- for i in xrange(ntesters)]
+ for i in range(ntesters)]
if ntesters:
subsys.tester = testers
subsys.checkers = checkers
@@ -264,8 +265,8 @@
# Create and connect the caches, both the ones fanning out
# to create the tree, and the ones used to connect testers
# on this level
- tree_caches = [prototypes[0]() for i in xrange(ncaches[0])]
- tester_caches = [proto_l1() for i in xrange(ntesters)]
+ tree_caches = [prototypes[0]() for i in range(ncaches[0])]
+ tester_caches = [proto_l1() for i in range(ntesters)]
subsys.cache = tester_caches + tree_caches
for cache in tree_caches:
diff --git a/configs/example/memtest.py b/configs/example/memtest.py
index d293164..1bbedfd 100644
--- a/configs/example/memtest.py
+++ b/configs/example/memtest.py
@@ -40,6 +40,7 @@
# Andreas Hansson
from __future__ import print_function
+from __future__ import absolute_import
import optparse
import random
@@ -257,7 +258,7 @@
limit = (len(cachespec) - level + 1) * 100000000
testers = [proto_tester(interval = 10 * (level * level + 1),
progress_check = limit) \
- for i in xrange(ntesters)]
+ for i in range(ntesters)]
if ntesters:
subsys.tester = testers
@@ -272,8 +273,8 @@
# Create and connect the caches, both the ones fanning out
# to create the tree, and the ones used to connect testers
# on this level
- tree_caches = [prototypes[0]() for i in xrange(ncaches[0])]
- tester_caches = [proto_l1() for i in xrange(ntesters)]
+ tree_caches = [prototypes[0]() for i in range(ncaches[0])]
+ tester_caches = [proto_l1() for i in range(ntesters)]
subsys.cache = tester_caches + tree_caches
for cache in tree_caches:
diff --git a/configs/example/read_config.py b/configs/example/read_config.py
index 3c17d4b..6ab5a81 100644
--- a/configs/example/read_config.py
+++ b/configs/example/read_config.py
@@ -46,6 +46,7 @@
# debugging.
from __future__ import print_function
+from __future__ import absolute_import
import argparse
import ConfigParser
@@ -280,7 +281,7 @@
# Assume that unnamed ports are unconnected
peers = self.config.get_port_peers(object_name, port_name)
- for index, peer in zip(xrange(0, len(peers)), peers):
+ for index, peer in zip(range(0, len(peers)), peers):
parsed_ports.append((
PortConnection(object_name, port.name, index),
PortConnection.from_string(peer)))
diff --git a/configs/example/ruby_direct_test.py
b/configs/example/ruby_direct_test.py
index 317fb47..d69df6e 100644
--- a/configs/example/ruby_direct_test.py
+++ b/configs/example/ruby_direct_test.py
@@ -29,6 +29,7 @@
# Brad Beckmann
from __future__ import print_function
+from __future__ import absolute_import
import m5
from m5.objects import *
diff --git a/configs/example/ruby_gpu_random_test.py
b/configs/example/ruby_gpu_random_test.py
index 162d3ff..35a412a 100644
--- a/configs/example/ruby_gpu_random_test.py
+++ b/configs/example/ruby_gpu_random_test.py
@@ -32,6 +32,7 @@
# Authors: Brad Beckmann
from __future__ import print_function
+from __future__ import absolute_import
import m5
from m5.objects import *
@@ -76,7 +77,9 @@
#
Ruby.define_options(parser)
-execfile(os.path.join(config_root, "common", "Options.py"))
+exec(compile( \
+ open(os.path.join(config_root, "common", "Options.py")).read(), \
+ os.path.join(config_root, "common", "Options.py"), 'exec'))
(options, args) = parser.parse_args()
diff --git a/configs/example/ruby_mem_test.py
b/configs/example/ruby_mem_test.py
index 68ad1ca..592ab1c 100644
--- a/configs/example/ruby_mem_test.py
+++ b/configs/example/ruby_mem_test.py
@@ -29,6 +29,7 @@
# Brad Beckmann
from __future__ import print_function
+from __future__ import absolute_import
import m5
from m5.objects import *
@@ -65,7 +66,9 @@
#
Ruby.define_options(parser)
-execfile(os.path.join(config_root, "common", "Options.py"))
+exec(compile( \
+ open(os.path.join(config_root, "common", "Options.py")).read(), \
+ os.path.join(config_root, "common", "Options.py"), 'exec'))
(options, args) = parser.parse_args()
@@ -101,7 +104,7 @@
percent_uncacheable = 0,
progress_interval = options.progress,
suppress_func_warnings = options.suppress_func_warnings) \
- for i in xrange(options.num_cpus) ]
+ for i in range(options.num_cpus) ]
system = System(cpu = cpus,
clk_domain = SrcClockDomain(clock = options.sys_clock),
@@ -114,7 +117,7 @@
progress_interval = options.progress,
suppress_func_warnings =
not
options.suppress_func_warnings) \
- for i in xrange(options.num_dmas) ]
+ for i in range(options.num_dmas) ]
system.dma_devices = dmas
else:
dmas = []
diff --git a/configs/example/ruby_random_test.py
b/configs/example/ruby_random_test.py
index d6b53cf..982557e 100644
--- a/configs/example/ruby_random_test.py
+++ b/configs/example/ruby_random_test.py
@@ -29,6 +29,7 @@
# Brad Beckmann
from __future__ import print_function
+from __future__ import absolute_import
import m5
from m5.objects import *
@@ -59,7 +60,9 @@
#
Ruby.define_options(parser)
-execfile(os.path.join(config_root, "common", "Options.py"))
+exec(compile( \
+ open(os.path.join(config_root, "common", "Options.py")).read(), \
+ os.path.join(config_root, "common", "Options.py"), 'exec'))
(options, args) = parser.parse_args()
diff --git a/configs/example/se.py b/configs/example/se.py
index 8403066..9de1c0f 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -43,6 +43,7 @@
# "m5 test.py"
from __future__ import print_function
+from __future__ import absolute_import
import optparse
import sys
@@ -171,7 +172,7 @@
fatal("You cannot use SMT with multiple CPUs!")
np = options.num_cpus
-system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
+system = System(cpu = [CPUClass(cpu_id=i) for i in range(np)],
mem_mode = test_mem_mode,
mem_ranges = [AddrRange(options.mem_size)],
cache_line_size = options.cacheline_size)
@@ -220,7 +221,7 @@
if np > 1:
fatal("SimPoint generation not supported with more than one CPUs")
-for i in xrange(np):
+for i in range(np):
if options.smt:
system.cpu[i].workload = multiprocesses
elif len(multiprocesses) == 1:
@@ -246,7 +247,7 @@
system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
voltage_domain =
system.voltage_domain)
- for i in xrange(np):
+ for i in range(np):
ruby_port = system.ruby._cpu_ports[i]
# Create the interrupt controller and connect its ports to Ruby
diff --git a/configs/learning_gem5/part1/caches.py
b/configs/learning_gem5/part1/caches.py
index 5183c13..5e87c2b 100644
--- a/configs/learning_gem5/part1/caches.py
+++ b/configs/learning_gem5/part1/caches.py
@@ -33,6 +33,10 @@
gem5 configuration script. It uses the SimpleOpts wrapper to set up command
line options from each individual class.
"""
+
+from __future__ import print_function
+from __future__ import absolute_import
+
import m5
from m5.objects import Cache
diff --git a/configs/learning_gem5/part1/simple.py
b/configs/learning_gem5/part1/simple.py
index 5336b44..c624de0 100644
--- a/configs/learning_gem5/part1/simple.py
+++ b/configs/learning_gem5/part1/simple.py
@@ -38,6 +38,8 @@
"""
from __future__ import print_function
+from __future__ import absolute_import
+
# import the m5 (gem5) library created when gem5 is built
import m5
diff --git a/configs/learning_gem5/part1/two_level.py
b/configs/learning_gem5/part1/two_level.py
index 51d51c4..b6f8781 100644
--- a/configs/learning_gem5/part1/two_level.py
+++ b/configs/learning_gem5/part1/two_level.py
@@ -41,6 +41,7 @@
"""
from __future__ import print_function
+from __future__ import absolute_import
# import the m5 (gem5) library created when gem5 is built
import m5
diff --git a/configs/learning_gem5/part2/hello_goodbye.py
b/configs/learning_gem5/part2/hello_goodbye.py
index e908ae0..e5ee5e7 100644
--- a/configs/learning_gem5/part2/hello_goodbye.py
+++ b/configs/learning_gem5/part2/hello_goodbye.py
@@ -37,6 +37,7 @@
"""
from __future__ import print_function
+from __future__ import absolute_import
# import the m5 (gem5) library created when gem5 is built
import m5
diff --git a/configs/learning_gem5/part2/run_simple.py
b/configs/learning_gem5/part2/run_simple.py
index 1b729ae..7940c0e 100644
--- a/configs/learning_gem5/part2/run_simple.py
+++ b/configs/learning_gem5/part2/run_simple.py
@@ -36,6 +36,7 @@
"""
from __future__ import print_function
+from __future__ import absolute_import
# import the m5 (gem5) library created when gem5 is built
import m5
diff --git a/configs/learning_gem5/part2/simple_cache.py
b/configs/learning_gem5/part2/simple_cache.py
index 98078df..c650242 100644
--- a/configs/learning_gem5/part2/simple_cache.py
+++ b/configs/learning_gem5/part2/simple_cache.py
@@ -34,6 +34,7 @@
"""
from __future__ import print_function
+from __future__ import absolute_import
# import the m5 (gem5) library created when gem5 is built
import m5
diff --git a/configs/learning_gem5/part2/simple_memobj.py
b/configs/learning_gem5/part2/simple_memobj.py
index 066bca0..24c6a24 100644
--- a/configs/learning_gem5/part2/simple_memobj.py
+++ b/configs/learning_gem5/part2/simple_memobj.py
@@ -34,6 +34,7 @@
"""
from __future__ import print_function
+from __future__ import absolute_import
# import the m5 (gem5) library created when gem5 is built
import m5
diff --git a/configs/learning_gem5/part3/msi_caches.py
b/configs/learning_gem5/part3/msi_caches.py
index 7bd24ef..42ec95a 100644
--- a/configs/learning_gem5/part3/msi_caches.py
+++ b/configs/learning_gem5/part3/msi_caches.py
@@ -36,6 +36,9 @@
"""
+from __future__ import print_function
+from __future__ import absolute_import
+
import math
from m5.defines import buildEnv
diff --git a/configs/learning_gem5/part3/ruby_caches_MI_example.py
b/configs/learning_gem5/part3/ruby_caches_MI_example.py
index 104f0df..db39bac 100644
--- a/configs/learning_gem5/part3/ruby_caches_MI_example.py
+++ b/configs/learning_gem5/part3/ruby_caches_MI_example.py
@@ -38,6 +38,9 @@
"""
+from __future__ import print_function
+from __future__ import absolute_import
+
import math
from m5.defines import buildEnv
diff --git a/configs/learning_gem5/part3/ruby_test.py
b/configs/learning_gem5/part3/ruby_test.py
index 692a87e..45c139b 100644
--- a/configs/learning_gem5/part3/ruby_test.py
+++ b/configs/learning_gem5/part3/ruby_test.py
@@ -35,13 +35,14 @@
"""
from __future__ import print_function
+from __future__ import absolute_import
# import the m5 (gem5) library created when gem5 is built
import m5
# import all of the SimObjects
from m5.objects import *
-from test_caches import TestCacheSystem
+from .test_caches import TestCacheSystem
# create the system we are going to simulate
system = System()
diff --git a/configs/learning_gem5/part3/simple_ruby.py
b/configs/learning_gem5/part3/simple_ruby.py
index 9b89b78..dda9e6d 100644
--- a/configs/learning_gem5/part3/simple_ruby.py
+++ b/configs/learning_gem5/part3/simple_ruby.py
@@ -38,6 +38,7 @@
"""
from __future__ import print_function
+from __future__ import absolute_import
# import the m5 (gem5) library created when gem5 is built
import m5
@@ -46,7 +47,7 @@
# You can import ruby_caches_MI_example to use the MI_example protocol
instead
# of the MSI protocol
-from msi_caches import MyCacheSystem
+from .msi_caches import MyCacheSystem
# create the system we are going to simulate
system = System()
diff --git a/configs/learning_gem5/part3/test_caches.py
b/configs/learning_gem5/part3/test_caches.py
index 3721f4a..4b17250 100644
--- a/configs/learning_gem5/part3/test_caches.py
+++ b/configs/learning_gem5/part3/test_caches.py
@@ -36,12 +36,15 @@
"""
+from __future__ import print_function
+from __future__ import absolute_import
+
from m5.defines import buildEnv
from m5.util import fatal
from m5.objects import *
-from msi_caches import L1Cache, DirController, MyNetwork
+from .msi_caches import L1Cache, DirController, MyNetwork
class TestCacheSystem(RubySystem):
diff --git a/configs/network/Network.py b/configs/network/Network.py
index 567e6b0..c1e55bc 100644
--- a/configs/network/Network.py
+++ b/configs/network/Network.py
@@ -26,6 +26,9 @@
#
# Authors: Tushar Krishna
+from __future__ import print_function
+from __future__ import absolute_import
+
import math
import m5
from m5.objects import *
diff --git a/configs/network/__init__.py b/configs/network/__init__.py
index 1829385..32393d1 100644
--- a/configs/network/__init__.py
+++ b/configs/network/__init__.py
@@ -34,3 +34,6 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Andreas Hansson
+
+from __future__ import print_function
+from __future__ import absolute_import
diff --git a/configs/ruby/AMD_Base_Constructor.py
b/configs/ruby/AMD_Base_Constructor.py
index 96f6575..ff67c5b 100644
--- a/configs/ruby/AMD_Base_Constructor.py
+++ b/configs/ruby/AMD_Base_Constructor.py
@@ -115,7 +115,7 @@
cpu_sequencers = []
cpuCluster = None
cpuCluster = Cluster(name="CPU Cluster", extBW = 8, intBW=8) # 16 GB/s
- for i in xrange((options.num_cpus + 1) / 2):
+ for i in range((options.num_cpus + 1) / 2):
cp_cntrl = CPCntrl()
cp_cntrl.create(options, ruby_system, system)
diff --git a/configs/ruby/GPU_RfO.py b/configs/ruby/GPU_RfO.py
index fea5e5a..c9bda0b 100644
--- a/configs/ruby/GPU_RfO.py
+++ b/configs/ruby/GPU_RfO.py
@@ -36,8 +36,8 @@
from m5.objects import *
from m5.defines import buildEnv
from m5.util import addToPath
-from Ruby import create_topology
-from Ruby import send_evicts
+from .Ruby import create_topology
+from .Ruby import send_evicts
addToPath('../')
@@ -470,7 +470,7 @@
block_size_bits = int(math.log(options.cacheline_size, 2))
numa_bit = block_size_bits + dir_bits - 1
- for i in xrange(options.num_dirs):
+ for i in range(options.num_dirs):
dir_ranges = []
for r in system.mem_ranges:
addr_range = m5.objects.AddrRange(r.start, size = r.size(),
@@ -511,7 +511,7 @@
# For an odd number of CPUs, still create the right number of
controllers
cpuCluster = Cluster(extBW = 512, intBW = 512) # 1 TB/s
- for i in xrange((options.num_cpus + 1) / 2):
+ for i in range((options.num_cpus + 1) // 2):
cp_cntrl = CPCntrl()
cp_cntrl.create(options, ruby_system, system)
@@ -545,7 +545,7 @@
gpuCluster = Cluster(extBW = 512, intBW = 512) # 1 TB/s
- for i in xrange(options.num_compute_units):
+ for i in range(options.num_compute_units):
tcp_cntrl = TCPCntrl(TCC_select_num_bits = TCC_bits,
number_of_TBEs = 2560) # max outstanding
requests
@@ -578,7 +578,7 @@
gpuCluster.add(tcp_cntrl)
- for i in xrange(options.num_sqc):
+ for i in range(options.num_sqc):
sqc_cntrl = SQCCntrl(TCC_select_num_bits = TCC_bits)
sqc_cntrl.create(options, ruby_system, system)
@@ -610,7 +610,7 @@
# SQC also in GPU cluster
gpuCluster.add(sqc_cntrl)
- for i in xrange(options.num_cp):
+ for i in range(options.num_cp):
tcp_cntrl = TCPCntrl(TCC_select_num_bits = TCC_bits,
number_of_TBEs = 2560) # max outstanding
requests
@@ -673,7 +673,7 @@
# SQC also in GPU cluster
gpuCluster.add(sqc_cntrl)
- for i in xrange(options.num_tccs):
+ for i in range(options.num_tccs):
tcc_cntrl = TCCCntrl(TCC_select_num_bits = TCC_bits,
number_of_TBEs = options.num_compute_units *
2560)
diff --git a/configs/ruby/GPU_VIPER.py b/configs/ruby/GPU_VIPER.py
index 8d12230..4121e21 100644
--- a/configs/ruby/GPU_VIPER.py
+++ b/configs/ruby/GPU_VIPER.py
@@ -429,7 +429,7 @@
mainCluster = Cluster(intBW=crossbar_bw)
else:
mainCluster = Cluster(intBW=8) # 16 GB/s
- for i in xrange(options.num_dirs):
+ for i in range(options.num_dirs):
dir_cntrl = DirCntrl(noTCCdir = True, TCC_select_num_bits =
TCC_bits)
dir_cntrl.create(options, ruby_system, system)
@@ -467,7 +467,7 @@
cpuCluster = Cluster(extBW = crossbar_bw, intBW = crossbar_bw)
else:
cpuCluster = Cluster(extBW = 8, intBW = 8) # 16 GB/s
- for i in xrange((options.num_cpus + 1) / 2):
+ for i in range((options.num_cpus + 1) / 2):
cp_cntrl = CPCntrl()
cp_cntrl.create(options, ruby_system, system)
@@ -504,7 +504,7 @@
gpuCluster = Cluster(extBW = crossbar_bw, intBW = crossbar_bw)
else:
gpuCluster = Cluster(extBW = 8, intBW = 8) # 16 GB/s
- for i in xrange(options.num_compute_units):
+ for i in range(options.num_compute_units):
tcp_cntrl = TCPCntrl(TCC_select_num_bits = TCC_bits,
issue_latency = 1,
@@ -543,7 +543,7 @@
gpuCluster.add(tcp_cntrl)
- for i in xrange(options.num_sqc):
+ for i in range(options.num_sqc):
sqc_cntrl = SQCCntrl(TCC_select_num_bits = TCC_bits)
sqc_cntrl.create(options, ruby_system, system)
@@ -569,7 +569,7 @@
# SQC also in GPU cluster
gpuCluster.add(sqc_cntrl)
- for i in xrange(options.num_cp):
+ for i in range(options.num_cp):
tcp_ID = options.num_compute_units + i
sqc_ID = options.num_sqc + i
@@ -623,7 +623,7 @@
# SQC also in GPU cluster
gpuCluster.add(sqc_cntrl)
- for i in xrange(options.num_tccs):
+ for i in range(options.num_tccs):
tcc_cntrl = TCCCntrl(l2_response_latency = options.TCC_latency)
tcc_cntrl.create(options, ruby_system, system)
diff --git a/configs/ruby/GPU_VIPER_Baseline.py
b/configs/ruby/GPU_VIPER_Baseline.py
index 960cbbd..3cfbc51 100644
--- a/configs/ruby/GPU_VIPER_Baseline.py
+++ b/configs/ruby/GPU_VIPER_Baseline.py
@@ -407,7 +407,7 @@
# Clusters
crossbar_bw = 16 * options.num_compute_units #Assuming a 2GHz clock
mainCluster = Cluster(intBW = crossbar_bw)
- for i in xrange(options.num_dirs):
+ for i in range(options.num_dirs):
dir_cntrl = DirCntrl(noTCCdir=True,TCC_select_num_bits = TCC_bits)
dir_cntrl.create(options, ruby_system, system)
@@ -440,7 +440,7 @@
mainCluster.add(dir_cntrl)
cpuCluster = Cluster(extBW = crossbar_bw, intBW=crossbar_bw)
- for i in xrange((options.num_cpus + 1) / 2):
+ for i in range((options.num_cpus + 1) / 2):
cp_cntrl = CPCntrl()
cp_cntrl.create(options, ruby_system, system)
@@ -473,7 +473,7 @@
cpuCluster.add(cp_cntrl)
gpuCluster = Cluster(extBW = crossbar_bw, intBW = crossbar_bw)
- for i in xrange(options.num_compute_units):
+ for i in range(options.num_compute_units):
tcp_cntrl = TCPCntrl(TCC_select_num_bits = TCC_bits,
issue_latency = 1,
@@ -510,7 +510,7 @@
gpuCluster.add(tcp_cntrl)
- for i in xrange(options.num_sqc):
+ for i in range(options.num_sqc):
sqc_cntrl = SQCCntrl(TCC_select_num_bits = TCC_bits)
sqc_cntrl.create(options, ruby_system, system)
@@ -539,7 +539,7 @@
# Because of wire buffers, num_tccs must equal num_tccdirs
numa_bit = 6
- for i in xrange(options.num_tccs):
+ for i in range(options.num_tccs):
tcc_cntrl = TCCCntrl()
tcc_cntrl.create(options, ruby_system, system)
diff --git a/configs/ruby/GPU_VIPER_Region.py
b/configs/ruby/GPU_VIPER_Region.py
index 90e8b77..10b1c28 100644
--- a/configs/ruby/GPU_VIPER_Region.py
+++ b/configs/ruby/GPU_VIPER_Region.py
@@ -469,7 +469,7 @@
# For an odd number of CPUs, still create the right number of
controllers
crossbar_bw = 16 * options.num_compute_units #Assuming a 2GHz clock
cpuCluster = Cluster(extBW = (crossbar_bw), intBW=crossbar_bw)
- for i in xrange((options.num_cpus + 1) / 2):
+ for i in range((options.num_cpus + 1) / 2):
cp_cntrl = CPCntrl()
cp_cntrl.create(options, ruby_system, system)
@@ -535,7 +535,7 @@
cpuCluster.add(rb_cntrl)
gpuCluster = Cluster(extBW = (crossbar_bw), intBW = crossbar_bw)
- for i in xrange(options.num_compute_units):
+ for i in range(options.num_compute_units):
tcp_cntrl = TCPCntrl(TCC_select_num_bits = TCC_bits,
issue_latency = 1,
@@ -571,7 +571,7 @@
gpuCluster.add(tcp_cntrl)
- for i in xrange(options.num_sqc):
+ for i in range(options.num_sqc):
sqc_cntrl = SQCCntrl(TCC_select_num_bits = TCC_bits)
sqc_cntrl.create(options, ruby_system, system)
@@ -599,7 +599,7 @@
numa_bit = 6
- for i in xrange(options.num_tccs):
+ for i in range(options.num_tccs):
tcc_cntrl = TCCCntrl()
tcc_cntrl.create(options, ruby_system, system)
diff --git a/configs/ruby/Garnet_standalone.py
b/configs/ruby/Garnet_standalone.py
index a70780b..c38bdba 100644
--- a/configs/ruby/Garnet_standalone.py
+++ b/configs/ruby/Garnet_standalone.py
@@ -66,7 +66,7 @@
# controller constructors are called before the network constructor
#
- for i in xrange(options.num_cpus):
+ for i in range(options.num_cpus):
#
# First create the Ruby objects associated with this cpu
# Only one cache exists for this protocol, so by default use the
L1D
diff --git a/configs/ruby/MESI_Three_Level.py
b/configs/ruby/MESI_Three_Level.py
index f38b7cf..95ac342 100644
--- a/configs/ruby/MESI_Three_Level.py
+++ b/configs/ruby/MESI_Three_Level.py
@@ -83,8 +83,8 @@
# Must create the individual controllers before the network to ensure
the
# controller constructors are called before the network constructor
#
- for i in xrange(options.num_clusters):
- for j in xrange(num_cpus_per_cluster):
+ for i in range(options.num_clusters):
+ for j in range(num_cpus_per_cluster):
#
# First create the Ruby objects associated with this cpu
#
@@ -164,7 +164,7 @@
l1_cntrl.responseFromL2.slave = ruby_system.network.master
- for j in xrange(num_l2caches_per_cluster):
+ for j in range(num_l2caches_per_cluster):
l2_cache = L2Cache(size = options.l2_size,
assoc = options.l2_assoc,
start_index_bit = l2_index_start)
diff --git a/configs/ruby/MESI_Two_Level.py b/configs/ruby/MESI_Two_Level.py
index 52976e6..27ef9c8 100644
--- a/configs/ruby/MESI_Two_Level.py
+++ b/configs/ruby/MESI_Two_Level.py
@@ -67,7 +67,7 @@
l2_bits = int(math.log(options.num_l2caches, 2))
block_size_bits = int(math.log(options.cacheline_size, 2))
- for i in xrange(options.num_cpus):
+ for i in range(options.num_cpus):
#
# First create the Ruby objects associated with this cpu
#
@@ -135,7 +135,7 @@
l2_index_start = block_size_bits + l2_bits
- for i in xrange(options.num_l2caches):
+ for i in range(options.num_l2caches):
#
# First create the Ruby objects associated with this cpu
#
diff --git a/configs/ruby/MI_example.py b/configs/ruby/MI_example.py
index 222d084..5e3ec58 100644
--- a/configs/ruby/MI_example.py
+++ b/configs/ruby/MI_example.py
@@ -31,8 +31,8 @@
import m5
from m5.objects import *
from m5.defines import buildEnv
-from Ruby import create_topology, create_directories
-from Ruby import send_evicts
+from .Ruby import create_topology, create_directories
+from .Ruby import send_evicts
#
# Declare caches used by the protocol
@@ -64,7 +64,7 @@
#
block_size_bits = int(math.log(options.cacheline_size, 2))
- for i in xrange(options.num_cpus):
+ for i in range(options.num_cpus):
#
# First create the Ruby objects associated with this cpu
# Only one cache exists for this protocol, so by default use the
L1D
diff --git a/configs/ruby/MOESI_AMD_Base.py b/configs/ruby/MOESI_AMD_Base.py
index ad16543..789bff0 100644
--- a/configs/ruby/MOESI_AMD_Base.py
+++ b/configs/ruby/MOESI_AMD_Base.py
@@ -248,7 +248,7 @@
block_size_bits = int(math.log(options.cacheline_size, 2))
numa_bit = block_size_bits + dir_bits - 1
- for i in xrange(options.num_dirs):
+ for i in range(options.num_dirs):
dir_ranges = []
for r in system.mem_ranges:
addr_range = m5.objects.AddrRange(r.start, size = r.size(),
@@ -294,7 +294,7 @@
# For an odd number of CPUs, still create the right number of
controllers
cpuCluster = Cluster(extBW = 512, intBW = 512) # 1 TB/s
- for i in xrange((options.num_cpus + 1) / 2):
+ for i in range((options.num_cpus + 1) / 2):
cp_cntrl = CPCntrl()
cp_cntrl.create(options, ruby_system, system)
diff --git a/configs/ruby/MOESI_CMP_directory.py
b/configs/ruby/MOESI_CMP_directory.py
index 3fef48b..40cb7ce 100644
--- a/configs/ruby/MOESI_CMP_directory.py
+++ b/configs/ruby/MOESI_CMP_directory.py
@@ -67,7 +67,7 @@
l2_bits = int(math.log(options.num_l2caches, 2))
block_size_bits = int(math.log(options.cacheline_size, 2))
- for i in xrange(options.num_cpus):
+ for i in range(options.num_cpus):
#
# First create the Ruby objects associated with this cpu
#
@@ -126,7 +126,7 @@
l2_index_start = block_size_bits + l2_bits
- for i in xrange(options.num_l2caches):
+ for i in range(options.num_l2caches):
#
# First create the Ruby objects associated with this cpu
#
diff --git a/configs/ruby/MOESI_CMP_token.py
b/configs/ruby/MOESI_CMP_token.py
index 94a518b..817d6f9 100644
--- a/configs/ruby/MOESI_CMP_token.py
+++ b/configs/ruby/MOESI_CMP_token.py
@@ -80,7 +80,7 @@
l2_bits = int(math.log(options.num_l2caches, 2))
block_size_bits = int(math.log(options.cacheline_size, 2))
- for i in xrange(options.num_cpus):
+ for i in range(options.num_cpus):
#
# First create the Ruby objects associated with this cpu
#
@@ -149,7 +149,7 @@
l2_index_start = block_size_bits + l2_bits
- for i in xrange(options.num_l2caches):
+ for i in range(options.num_l2caches):
#
# First create the Ruby objects associated with this cpu
#
diff --git a/configs/ruby/MOESI_hammer.py b/configs/ruby/MOESI_hammer.py
index 7c31ca2..7630886 100644
--- a/configs/ruby/MOESI_hammer.py
+++ b/configs/ruby/MOESI_hammer.py
@@ -74,7 +74,7 @@
#
block_size_bits = int(math.log(options.cacheline_size, 2))
- for i in xrange(options.num_cpus):
+ for i in range(options.num_cpus):
#
# First create the Ruby objects associated with this cpu
#
diff --git a/configs/ruby/Ruby.py b/configs/ruby/Ruby.py
index 2ddf608..ffa5a02 100644
--- a/configs/ruby/Ruby.py
+++ b/configs/ruby/Ruby.py
@@ -81,7 +81,7 @@
help="Recycle latency for ruby controller input
buffers")
protocol = buildEnv['PROTOCOL']
- exec "import %s" % protocol
+ exec("from . import %s" % protocol)
eval("%s.define_options(parser)" % protocol)
Network.define_options(parser)
@@ -144,7 +144,7 @@
found in configs/topologies/BaseTopology.py
This is a wrapper for the legacy topologies.
"""
- exec "import topologies.%s as Topo" % options.topology
+ exec("import topologies.%s as Topo" % options.topology)
topology = eval("Topo.%s(controllers)" % options.topology)
return topology
@@ -160,7 +160,7 @@
ruby.network = network
protocol = buildEnv['PROTOCOL']
- exec "import %s" % protocol
+ exec("from . import %s" % protocol)
try:
(cpu_sequencers, dir_cntrls, topology) = \
eval("%s.create_system(options, full_system, system,
dma_ports,\
@@ -214,7 +214,7 @@
def create_directories(options, bootmem, ruby_system, system):
dir_cntrl_nodes = []
- for i in xrange(options.num_dirs):
+ for i in range(options.num_dirs):
dir_cntrl = Directory_Controller()
dir_cntrl.version = i
dir_cntrl.directory = RubyDirectoryMemory()
diff --git a/configs/splash2/cluster.py b/configs/splash2/cluster.py
index f819bd1..04195cc 100644
--- a/configs/splash2/cluster.py
+++ b/configs/splash2/cluster.py
@@ -31,6 +31,7 @@
# "m5 test.py"
from __future__ import print_function
+from __future__ import absolute_import
import os
import optparse
@@ -167,41 +168,41 @@
all_l1s = []
all_l1buses = []
if options.timing:
- clusters = [ Cluster() for i in xrange(options.numclusters)]
- for j in xrange(options.numclusters):
+ clusters = [ Cluster() for i in range(options.numclusters)]
+ for j in range(options.numclusters):
clusters[j].id = j
for cluster in clusters:
cluster.clusterbus = L2XBar(clock=busFrequency)
all_l1buses += [cluster.clusterbus]
cluster.cpus = [TimingSimpleCPU(cpu_id = i + cluster.id,
clock=options.frequency)
- for i in xrange(cpusPerCluster)]
+ for i in range(cpusPerCluster)]
all_cpus += cluster.cpus
cluster.l1 = L1(size=options.l1size, assoc = 4)
all_l1s += [cluster.l1]
elif options.detailed:
- clusters = [ Cluster() for i in xrange(options.numclusters)]
- for j in xrange(options.numclusters):
+ clusters = [ Cluster() for i in range(options.numclusters)]
+ for j in range(options.numclusters):
clusters[j].id = j
for cluster in clusters:
cluster.clusterbus = L2XBar(clock=busFrequency)
all_l1buses += [cluster.clusterbus]
cluster.cpus = [DerivO3CPU(cpu_id = i + cluster.id,
clock=options.frequency)
- for i in xrange(cpusPerCluster)]
+ for i in range(cpusPerCluster)]
all_cpus += cluster.cpus
cluster.l1 = L1(size=options.l1size, assoc = 4)
all_l1s += [cluster.l1]
else:
- clusters = [ Cluster() for i in xrange(options.numclusters)]
- for j in xrange(options.numclusters):
+ clusters = [ Cluster() for i in range(options.numclusters)]
+ for j in range(options.numclusters):
clusters[j].id = j
for cluster in clusters:
cluster.clusterbus = L2XBar(clock=busFrequency)
all_l1buses += [cluster.clusterbus]
cluster.cpus = [AtomicSimpleCPU(cpu_id = i + cluster.id,
clock=options.frequency)
- for i in xrange(cpusPerCluster)]
+ for i in range(cpusPerCluster)]
all_cpus += cluster.cpus
cluster.l1 = L1(size=options.l1size, assoc = 4)
all_l1s += [cluster.l1]
diff --git a/configs/splash2/run.py b/configs/splash2/run.py
index b17eb54..c742664 100644
--- a/configs/splash2/run.py
+++ b/configs/splash2/run.py
@@ -30,6 +30,7 @@
#
from __future__ import print_function
+from __future__ import absolute_import
import os
import optparse
@@ -182,15 +183,15 @@
if options.timing:
cpus = [TimingSimpleCPU(cpu_id = i,
clock=options.frequency)
- for i in xrange(options.numcpus)]
+ for i in range(options.numcpus)]
elif options.detailed:
cpus = [DerivO3CPU(cpu_id = i,
clock=options.frequency)
- for i in xrange(options.numcpus)]
+ for i in range(options.numcpus)]
else:
cpus = [AtomicSimpleCPU(cpu_id = i,
clock=options.frequency)
- for i in xrange(options.numcpus)]
+ for i in range(options.numcpus)]
# ----------------------
# Create a system, and add system wide objects
diff --git a/configs/topologies/BaseTopology.py
b/configs/topologies/BaseTopology.py
index bd8ae25..180d437 100644
--- a/configs/topologies/BaseTopology.py
+++ b/configs/topologies/BaseTopology.py
@@ -26,6 +26,9 @@
#
# Authors: Jason Power
+from __future__ import print_function
+from __future__ import absolute_import
+
import m5
class BaseTopology(object):
diff --git a/configs/topologies/Cluster.py b/configs/topologies/Cluster.py
index 2116479..a0e7df6 100644
--- a/configs/topologies/Cluster.py
+++ b/configs/topologies/Cluster.py
@@ -26,8 +26,10 @@
#
# Authors: Jason Power
+from __future__ import print_function
+from __future__ import absolute_import
-from BaseTopology import BaseTopology
+from .BaseTopology import BaseTopology
class Cluster(BaseTopology):
""" A cluster is a group of nodes which are all one hop from eachother
diff --git a/configs/topologies/Crossbar.py b/configs/topologies/Crossbar.py
index 447b1c5..d545d54 100644
--- a/configs/topologies/Crossbar.py
+++ b/configs/topologies/Crossbar.py
@@ -26,10 +26,13 @@
#
# Authors: Steve Reinhardt
+from __future__ import print_function
+from __future__ import absolute_import
+
from m5.params import *
from m5.objects import *
-from BaseTopology import SimpleTopology
+from .BaseTopology import SimpleTopology
class Crossbar(SimpleTopology):
description='Crossbar'
diff --git a/configs/topologies/CrossbarGarnet.py
b/configs/topologies/CrossbarGarnet.py
index 64f8001..6322a31 100644
--- a/configs/topologies/CrossbarGarnet.py
+++ b/configs/topologies/CrossbarGarnet.py
@@ -26,10 +26,13 @@
#
# Authors: Tushar Krishna
+from __future__ import print_function
+from __future__ import absolute_import
+
from m5.params import *
from m5.objects import *
-from BaseTopology import SimpleTopology
+from .BaseTopology import SimpleTopology
class CrossbarGarnet(SimpleTopology):
description='CrossbarGarnet'
diff --git a/configs/topologies/MeshDirCorners_XY.py
b/configs/topologies/MeshDirCorners_XY.py
index 46f3c6f..95cb486 100644
--- a/configs/topologies/MeshDirCorners_XY.py
+++ b/configs/topologies/MeshDirCorners_XY.py
@@ -26,10 +26,13 @@
#
# Authors: Brad Beckmann
+from __future__ import print_function
+from __future__ import absolute_import
+
from m5.params import *
from m5.objects import *
-from BaseTopology import SimpleTopology
+from .BaseTopology import SimpleTopology
# Creates a Mesh topology with 4 directories, one at each corner.
# One L1 (and L2, depending on the protocol) are connected to each router.
@@ -126,8 +129,8 @@
int_links = []
# East output to West input links (weight = 1)
- for row in xrange(num_rows):
- for col in xrange(num_columns):
+ for row in range(num_rows):
+ for col in range(num_columns):
if (col + 1 < num_columns):
east_out = col + (row * num_columns)
west_in = (col + 1) + (row * num_columns)
@@ -141,8 +144,8 @@
link_count += 1
# West output to East input links (weight = 1)
- for row in xrange(num_rows):
- for col in xrange(num_columns):
+ for row in range(num_rows):
+ for col in range(num_columns):
if (col + 1 < num_columns):
east_in = col + (row * num_columns)
west_out = (col + 1) + (row * num_columns)
@@ -156,8 +159,8 @@
link_count += 1
# North output to South input links (weight = 2)
- for col in xrange(num_columns):
- for row in xrange(num_rows):
+ for col in range(num_columns):
+ for row in range(num_rows):
if (row + 1 < num_rows):
north_out = col + (row * num_columns)
south_in = col + ((row + 1) * num_columns)
@@ -171,8 +174,8 @@
link_count += 1
# South output to North input links (weight = 2)
- for col in xrange(num_columns):
- for row in xrange(num_rows):
+ for col in range(num_columns):
+ for row in range(num_rows):
if (row + 1 < num_rows):
north_in = col + (row * num_columns)
south_out = col + ((row + 1) * num_columns)
diff --git a/configs/topologies/Mesh_XY.py b/configs/topologies/Mesh_XY.py
index 652ac16..79575b3 100644
--- a/configs/topologies/Mesh_XY.py
+++ b/configs/topologies/Mesh_XY.py
@@ -28,10 +28,13 @@
# Authors: Brad Beckmann
# Tushar Krishna
+from __future__ import print_function
+from __future__ import absolute_import
+
from m5.params import *
from m5.objects import *
-from BaseTopology import SimpleTopology
+from .BaseTopology import SimpleTopology
# Creates a generic Mesh assuming an equal number of cache
# and directory controllers.
@@ -78,7 +81,7 @@
# distributed across the network.
network_nodes = []
remainder_nodes = []
- for node_index in xrange(len(nodes)):
+ for node_index in range(len(nodes)):
if node_index < (len(nodes) - remainder):
network_nodes.append(nodes[node_index])
else:
@@ -110,8 +113,8 @@
int_links = []
# East output to West input links (weight = 1)
- for row in xrange(num_rows):
- for col in xrange(num_columns):
+ for row in range(num_rows):
+ for col in range(num_columns):
if (col + 1 < num_columns):
east_out = col + (row * num_columns)
west_in = (col + 1) + (row * num_columns)
@@ -125,8 +128,8 @@
link_count += 1
# West output to East input links (weight = 1)
- for row in xrange(num_rows):
- for col in xrange(num_columns):
+ for row in range(num_rows):
+ for col in range(num_columns):
if (col + 1 < num_columns):
east_in = col + (row * num_columns)
west_out = (col + 1) + (row * num_columns)
@@ -140,8 +143,8 @@
link_count += 1
# North output to South input links (weight = 2)
- for col in xrange(num_columns):
- for row in xrange(num_rows):
+ for col in range(num_columns):
+ for row in range(num_rows):
if (row + 1 < num_rows):
north_out = col + (row * num_columns)
south_in = col + ((row + 1) * num_columns)
@@ -155,8 +158,8 @@
link_count += 1
# South output to North input links (weight = 2)
- for col in xrange(num_columns):
- for row in xrange(num_rows):
+ for col in range(num_columns):
+ for row in range(num_rows):
if (row + 1 < num_rows):
north_in = col + (row * num_columns)
south_out = col + ((row + 1) * num_columns)
diff --git a/configs/topologies/Mesh_westfirst.py
b/configs/topologies/Mesh_westfirst.py
index 6139f67..95cdae0 100644
--- a/configs/topologies/Mesh_westfirst.py
+++ b/configs/topologies/Mesh_westfirst.py
@@ -27,11 +27,13 @@
#
# Authors: Brad Beckmann
# Tushar Krishna
+from __future__ import print_function
+from __future__ import absolute_import
from m5.params import *
from m5.objects import *
-from BaseTopology import SimpleTopology
+from .BaseTopology import SimpleTopology
# Creates a generic Mesh assuming an equal number of cache
# and directory controllers.
@@ -82,7 +84,7 @@
# distributed across the network.
network_nodes = []
remainder_nodes = []
- for node_index in xrange(len(nodes)):
+ for node_index in range(len(nodes)):
if node_index < (len(nodes) - remainder):
network_nodes.append(nodes[node_index])
else:
@@ -114,8 +116,8 @@
int_links = []
# East output to West input links (weight = 2)
- for row in xrange(num_rows):
- for col in xrange(num_columns):
+ for row in range(num_rows):
+ for col in range(num_columns):
if (col + 1 < num_columns):
east_out = col + (row * num_columns)
west_in = (col + 1) + (row * num_columns)
@@ -127,8 +129,8 @@
link_count += 1
# West output to East input links (weight = 1)
- for row in xrange(num_rows):
- for col in xrange(num_columns):
+ for row in range(num_rows):
+ for col in range(num_columns):
if (col + 1 < num_columns):
east_in = col + (row * num_columns)
west_out = (col + 1) + (row * num_columns)
@@ -141,8 +143,8 @@
# North output to South input links (weight = 2)
- for col in xrange(num_columns):
- for row in xrange(num_rows):
+ for col in range(num_columns):
+ for row in range(num_rows):
if (row + 1 < num_rows):
north_out = col + (row * num_columns)
south_in = col + ((row + 1) * num_columns)
@@ -154,8 +156,8 @@
link_count += 1
# South output to North input links (weight = 2)
- for col in xrange(num_columns):
- for row in xrange(num_rows):
+ for col in range(num_columns):
+ for row in range(num_rows):
if (row + 1 < num_rows):
north_in = col + (row * num_columns)
south_out = col + ((row + 1) * num_columns)
diff --git a/configs/topologies/Pt2Pt.py b/configs/topologies/Pt2Pt.py
index 6cbf5ad..ce98dc5 100644
--- a/configs/topologies/Pt2Pt.py
+++ b/configs/topologies/Pt2Pt.py
@@ -28,10 +28,13 @@
# Authors: Brad Beckmann
# Tushar Krishna
+from __future__ import print_function
+from __future__ import absolute_import
+
from m5.params import *
from m5.objects import *
-from BaseTopology import SimpleTopology
+from .BaseTopology import SimpleTopology
class Pt2Pt(SimpleTopology):
description='Pt2Pt'
@@ -63,8 +66,8 @@
link_count = len(nodes)
int_links = []
- for i in xrange(len(nodes)):
- for j in xrange(len(nodes)):
+ for i in range(len(nodes)):
+ for j in range(len(nodes)):
if (i != j):
link_count += 1
int_links.append(IntLink(link_id=link_count,
diff --git a/configs/topologies/__init__.py b/configs/topologies/__init__.py
index 1829385..32393d1 100644
--- a/configs/topologies/__init__.py
+++ b/configs/topologies/__init__.py
@@ -34,3 +34,6 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Andreas Hansson
+
+from __future__ import print_function
+from __future__ import absolute_import
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Idcea8482b286779fc98b4e144ca8f54069c08024
Gerrit-Change-Number: 16002
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg <[email protected]>
Gerrit-MessageType: newchange
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