Austin Harris has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/16122 )
Change subject: riscv: Get rid of ISA specific register types in Interrupts.
......................................................................
riscv: Get rid of ISA specific register types in Interrupts.
Change-Id: I5542649c6af27a286f276a289b86c40dd7e32abc
Signed-off-by: Austin Harris <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/c/16122
Reviewed-by: Gabe Black <[email protected]>
Maintainer: Gabe Black <[email protected]>
---
M src/arch/riscv/interrupts.hh
1 file changed, 5 insertions(+), 5 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
diff --git a/src/arch/riscv/interrupts.hh b/src/arch/riscv/interrupts.hh
index 729af6f..912bf45 100644
--- a/src/arch/riscv/interrupts.hh
+++ b/src/arch/riscv/interrupts.hh
@@ -125,10 +125,10 @@
ip = 0;
}
- MiscReg readIP() const { return (MiscReg)ip.to_ulong(); }
- MiscReg readIE() const { return (MiscReg)ie.to_ulong(); }
- void setIP(const MiscReg& val) { ip = val; }
- void setIE(const MiscReg& val) { ie = val; }
+ uint64_t readIP() const { return (uint64_t)ip.to_ulong(); }
+ uint64_t readIE() const { return (uint64_t)ie.to_ulong(); }
+ void setIP(const uint64_t& val) { ip = val; }
+ void setIE(const uint64_t& val) { ie = val; }
void
serialize(CheckpointOut &cp)
@@ -150,4 +150,4 @@
} // namespace RiscvISA
-#endif // __ARCH_RISCV_INTERRUPT_HH__
\ No newline at end of file
+#endif // __ARCH_RISCV_INTERRUPT_HH__
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I5542649c6af27a286f276a289b86c40dd7e32abc
Gerrit-Change-Number: 16122
Gerrit-PatchSet: 3
Gerrit-Owner: Austin Harris <[email protected]>
Gerrit-Reviewer: Alec Roelke <[email protected]>
Gerrit-Reviewer: Austin Harris <[email protected]>
Gerrit-Reviewer: Gabe Black <[email protected]>
Gerrit-MessageType: merged
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