Jairo Balart has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/16222
Change subject: dev-arm: cleanup of gicv3 code
......................................................................
dev-arm: cleanup of gicv3 code
Change-Id: I9aba90022f6408838c4ab87c6b90bba438752e53
---
M src/dev/arm/gic_v3.cc
M src/dev/arm/gic_v3.hh
M src/dev/arm/gic_v3_cpu_interface.cc
M src/dev/arm/gic_v3_cpu_interface.hh
M src/dev/arm/gic_v3_distributor.cc
M src/dev/arm/gic_v3_distributor.hh
M src/dev/arm/gic_v3_redistributor.cc
M src/dev/arm/gic_v3_redistributor.hh
8 files changed, 637 insertions(+), 623 deletions(-)
diff --git a/src/dev/arm/gic_v3.cc b/src/dev/arm/gic_v3.cc
index 2fb90ea..a6bd3d8 100644
--- a/src/dev/arm/gic_v3.cc
+++ b/src/dev/arm/gic_v3.cc
@@ -45,10 +45,6 @@
{
}
-Gicv3::~Gicv3()
-{
-}
-
void
Gicv3::init()
{
@@ -112,7 +108,7 @@
"Invalid redistributor_id!");
panic_if(!redistributors[redistributor_id], "Redistributor is
null!");
resp = redistributors[redistributor_id]->read(daddr, size,
- is_secure_access);
+ is_secure_access);
delay = params()->redist_pio_delay;
DPRINTF(GIC, "Gicv3::read(): (redistributor %d) context_id %d "
"register %#x size %d is_secure_access %d (value %#x)\n",
@@ -179,7 +175,7 @@
void
Gicv3::clearInt(uint32_t number)
{
- distributor->intDeasserted(number);
+ distributor->deassertSPI(number);
}
void
@@ -201,7 +197,7 @@
void
Gicv3::postInt(uint32_t cpu, ArmISA::InterruptTypes int_type)
{
- postDelayedInt(cpu, int_type);
+ platform->intrctrl->post(cpu, int_type, 0);
}
void
@@ -210,14 +206,8 @@
platform->intrctrl->clear(cpu, int_type, 0);
}
-void
-Gicv3::postDelayedInt(uint32_t cpu, ArmISA::InterruptTypes int_type)
-{
- platform->intrctrl->post(cpu, int_type, 0);
-}
-
Gicv3Redistributor *
-Gicv3::getRedistributorByAffinity(uint32_t affinity)
+Gicv3::getRedistributorByAffinity(uint32_t affinity) const
{
for (auto & redistributor : redistributors) {
if (redistributor->getAffinity() == affinity) {
@@ -234,14 +224,12 @@
distributor->serializeSection(cp, "distributor");
for (uint32_t redistributor_id = 0;
- redistributor_id < redistributors.size();
- redistributor_id++)
+ redistributor_id < redistributors.size(); redistributor_id++)
redistributors[redistributor_id]->serializeSection(cp,
csprintf("redistributors.%i", redistributor_id));
for (uint32_t cpu_interface_id = 0;
- cpu_interface_id < cpuInterfaces.size();
- cpu_interface_id++)
+ cpu_interface_id < cpuInterfaces.size(); cpu_interface_id++)
cpuInterfaces[cpu_interface_id]->serializeSection(cp,
csprintf("cpuInterface.%i", cpu_interface_id));
}
@@ -254,14 +242,12 @@
distributor->unserializeSection(cp, "distributor");
for (uint32_t redistributor_id = 0;
- redistributor_id < redistributors.size();
- redistributor_id++)
+ redistributor_id < redistributors.size(); redistributor_id++)
redistributors[redistributor_id]->unserializeSection(cp,
csprintf("redistributors.%i", redistributor_id));
for (uint32_t cpu_interface_id = 0;
- cpu_interface_id < cpuInterfaces.size();
- cpu_interface_id++)
+ cpu_interface_id < cpuInterfaces.size(); cpu_interface_id++)
cpuInterfaces[cpu_interface_id]->unserializeSection(cp,
csprintf("cpuInterface.%i", cpu_interface_id));
}
diff --git a/src/dev/arm/gic_v3.hh b/src/dev/arm/gic_v3.hh
index a242639..19b65ae 100644
--- a/src/dev/arm/gic_v3.hh
+++ b/src/dev/arm/gic_v3.hh
@@ -34,14 +34,15 @@
#include "dev/arm/base_gic.hh"
#include "params/Gicv3.hh"
+class Gicv3CPUInterface;
class Gicv3Distributor;
class Gicv3Redistributor;
-class Gicv3CPUInterface;
class Gicv3 : public BaseGic
{
protected:
+ typedef Gicv3Params Params;
Gicv3Distributor * distributor;
std::vector<Gicv3Redistributor *> redistributors;
std::vector<Gicv3CPUInterface *> cpuInterfaces;
@@ -51,7 +52,7 @@
public:
- // Special interrupt IDs
+ // Special interrupt IDs, as per SPEC 2.2.1 section
static const int INTID_SECURE = 1020;
static const int INTID_NONSECURE = 1021;
static const int INTID_SPURIOUS = 1023;
@@ -61,6 +62,7 @@
// Number of Private Peripheral Interrupts
static const int PPI_MAX = 16;
+ // Interrupt states for PPIs, SGIs and SPIs, as per SPEC 4.1.2 section
typedef enum {
INT_INACTIVE,
INT_PENDING,
@@ -68,6 +70,7 @@
INT_ACTIVE_PENDING,
} IntStatus;
+ // Interrupt groups, as per SPEC section 4.6
typedef enum {
G0S,
G1S,
@@ -79,7 +82,19 @@
INT_EDGE_TRIGGERED,
} IntTriggerType;
- typedef Gicv3Params Params;
+ protected:
+
+ void clearInt(uint32_t int_id) override;
+ void clearPPInt(uint32_t int_id, uint32_t cpu) override;
+
+ inline AddrRangeList
+ getAddrRanges() const override
+ {
+ return addrRanges;
+ }
+
+ void init() override;
+ void initState() override;
const Params *
params() const
@@ -87,41 +102,33 @@
return dynamic_cast<const Params *>(_params);
}
- Gicv3(const Params * p);
- ~Gicv3();
- void init() override;
- void initState() override;
-
- AddrRangeList
- getAddrRanges() const override
- {
- return addrRanges;
- }
-
Tick read(PacketPtr pkt) override;
- Tick write(PacketPtr pkt) override;
+ void reset();
void sendInt(uint32_t int_id) override;
- void clearInt(uint32_t int_id) override;
void sendPPInt(uint32_t int_id, uint32_t cpu) override;
- void clearPPInt(uint32_t int_id, uint32_t cpu) override;
-
void serialize(CheckpointOut & cp) const override;
void unserialize(CheckpointIn & cp) override;
+ Tick write(PacketPtr pkt) override;
- Gicv3Distributor *
- getDistributor() const
- {
- return distributor;
- }
+ public:
- Gicv3CPUInterface *
+ Gicv3(const Params * p);
+ void deassertInt(uint32_t cpu, ArmISA::InterruptTypes int_type);
+
+ inline Gicv3CPUInterface *
getCPUInterface(int cpu_id) const
{
assert(cpu_id < cpuInterfaces.size() and cpuInterfaces[cpu_id]);
return cpuInterfaces[cpu_id];
}
- Gicv3Redistributor *
+ inline Gicv3Distributor *
+ getDistributor() const
+ {
+ return distributor;
+ }
+
+ inline Gicv3Redistributor *
getRedistributor(ContextID context_id) const
{
assert(context_id < redistributors.size() and
@@ -129,14 +136,9 @@
return redistributors[context_id];
}
- Gicv3Redistributor * getRedistributorByAffinity(uint32_t affinity);
+ Gicv3Redistributor *
+ getRedistributorByAffinity(uint32_t affinity) const;
void postInt(uint32_t cpu, ArmISA::InterruptTypes int_type);
- void postDelayedInt(uint32_t cpu, ArmISA::InterruptTypes int_type);
- void deassertInt(uint32_t cpu, ArmISA::InterruptTypes int_type);
-
- protected:
-
- void reset();
};
#endif //__DEV_ARM_GICV3_H__
diff --git a/src/dev/arm/gic_v3_cpu_interface.cc
b/src/dev/arm/gic_v3_cpu_interface.cc
index 9bc8cbd..6e4e57e 100644
--- a/src/dev/arm/gic_v3_cpu_interface.cc
+++ b/src/dev/arm/gic_v3_cpu_interface.cc
@@ -45,10 +45,6 @@
{
}
-Gicv3CPUInterface::~Gicv3CPUInterface()
-{
-}
-
void
Gicv3CPUInterface::init()
{
@@ -69,7 +65,7 @@
}
bool
-Gicv3CPUInterface::getHCREL2FMO()
+Gicv3CPUInterface::getHCREL2FMO() const
{
HCR hcr = isa->readMiscRegNoEffect(MISCREG_HCR_EL2);
@@ -83,7 +79,7 @@
}
bool
-Gicv3CPUInterface::getHCREL2IMO()
+Gicv3CPUInterface::getHCREL2IMO() const
{
HCR hcr = isa->readMiscRegNoEffect(MISCREG_HCR_EL2);
@@ -104,6 +100,7 @@
bool hcr_imo = getHCREL2IMO();
switch (misc_reg) {
+ // Active Priorities Group 1 Registers
case MISCREG_ICC_AP1R0:
case MISCREG_ICC_AP1R0_EL1: {
if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
@@ -115,17 +112,18 @@
case MISCREG_ICC_AP1R1:
case MISCREG_ICC_AP1R1_EL1:
-
// only implemented if supporting 6 or more bits of priority
+
case MISCREG_ICC_AP1R2:
case MISCREG_ICC_AP1R2_EL1:
-
// only implemented if supporting 7 or more bits of priority
+
case MISCREG_ICC_AP1R3:
case MISCREG_ICC_AP1R3_EL1:
// only implemented if supporting 7 or more bits of priority
return 0;
+ // Active Priorities Group 0 Registers
case MISCREG_ICC_AP0R0:
case MISCREG_ICC_AP0R0_EL1: {
if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
@@ -137,17 +135,18 @@
case MISCREG_ICC_AP0R1:
case MISCREG_ICC_AP0R1_EL1:
-
// only implemented if supporting 6 or more bits of priority
+
case MISCREG_ICC_AP0R2:
case MISCREG_ICC_AP0R2_EL1:
-
// only implemented if supporting 7 or more bits of priority
+
case MISCREG_ICC_AP0R3:
case MISCREG_ICC_AP0R3_EL1:
// only implemented if supporting 7 or more bits of priority
return 0;
+ // Interrupt Group 0 Enable register
case MISCREG_ICC_IGRPEN0:
case MISCREG_ICC_IGRPEN0_EL1: {
if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
@@ -157,6 +156,7 @@
break;
}
+ // Interrupt Group 1 Enable register
case MISCREG_ICC_IGRPEN1:
case MISCREG_ICC_IGRPEN1_EL1: {
if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
@@ -166,6 +166,7 @@
break;
}
+ // Interrupt Group 1 Enable register
case MISCREG_ICC_MGRPEN1:
case MISCREG_ICC_IGRPEN1_EL3: {
// EnableGrp1S and EnableGrp1NS are aliased with
@@ -189,24 +190,28 @@
break;
}
+ // Running Priority Register
case MISCREG_ICC_RPR:
case MISCREG_ICC_RPR_EL1: {
if ((currEL() == EL1) && !inSecureState() &&
- (hcr_imo || hcr_fmo)) {
+ (hcr_imo || hcr_fmo)) {
return readMiscReg(MISCREG_ICV_RPR_EL1);
}
uint8_t rprio = highestActivePriority();
if (haveEL(EL3) && !inSecureState() &&
- (isa->readMiscRegNoEffect(MISCREG_SCR_EL3) & (1U << 2)))
{
- /* NS GIC access and Group 0 is inaccessible to NS */
+ (isa->readMiscRegNoEffect(MISCREG_SCR_EL3) & (1U << 2))) {
+ // Spec section 4.8.1
+ // For Non-secure access to ICC_RPR_EL1 when SCR_EL3.FIQ == 1
if ((rprio & 0x80) == 0) {
- /* NS should not see priorities in the Secure half of the
- * range */
+ // If the current priority mask value is in the range of
+ // 0x00-0x7F a read access returns the value 0x0
rprio = 0;
} else if (rprio != 0xff) {
- /* Non-idle priority: show the Non-secure view of it */
+ // If the current priority mask value is in the range of
+ // 0x80-0xFF a read access returns the Non-secure read of
+ // the current value
rprio = (rprio << 1) & 0xff;
}
}
@@ -215,11 +220,13 @@
break;
}
+ // Virtual Running Priority Register
case MISCREG_ICV_RPR_EL1: {
value = virtualHighestActivePriority();
break;
}
+ // Highest Priority Pending Interrupt Register 0
case MISCREG_ICC_HPPIR0:
case MISCREG_ICC_HPPIR0_EL1: {
if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
@@ -230,6 +237,7 @@
break;
}
+ // Virtual Highest Priority Pending Interrupt Register 0
case MISCREG_ICV_HPPIR0_EL1: {
value = Gicv3::INTID_SPURIOUS;
int lr_idx = getHPPVILR();
@@ -248,6 +256,7 @@
break;
}
+ // Highest Priority Pending Interrupt Register 1
case MISCREG_ICC_HPPIR1:
case MISCREG_ICC_HPPIR1_EL1: {
if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
@@ -258,6 +267,7 @@
break;
}
+ // Virtual Highest Priority Pending Interrupt Register 1
case MISCREG_ICV_HPPIR1_EL1: {
value = Gicv3::INTID_SPURIOUS;
int lr_idx = getHPPVILR();
@@ -276,6 +286,7 @@
break;
}
+ // Binary Point Register 0
case MISCREG_ICC_BPR0:
case MISCREG_ICC_BPR0_EL1:
if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
@@ -284,6 +295,7 @@
M5_FALLTHROUGH;
+ // Binary Point Register 1
case MISCREG_ICC_BPR1:
case MISCREG_ICC_BPR1_EL1:
if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
@@ -299,18 +311,18 @@
}
if ((group == Gicv3::G1S) &&
- !isEL3OrMon() &&
- (isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S)
- & ICC_CTLR_EL1_CBPR)) {
+ !isEL3OrMon() &&
+ (isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S)
+ & ICC_CTLR_EL1_CBPR)) {
group = Gicv3::G0S;
}
bool sat_inc = false;
if ((group == Gicv3::G1NS) &&
- (currEL() < EL3) &&
- (isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS)
- & ICC_CTLR_EL1_CBPR)) {
+ (currEL() < EL3) &&
+ (isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS)
+ & ICC_CTLR_EL1_CBPR)) {
// Reads return BPR0 + 1 saturated to 7, WI
group = Gicv3::G0S;
sat_inc = true;
@@ -336,6 +348,7 @@
break;
}
+ // Virtual Binary Point Register 1
case MISCREG_ICV_BPR0_EL1:
case MISCREG_ICV_BPR1_EL1: {
Gicv3::GroupId group =
@@ -345,7 +358,7 @@
bool sat_inc = false;
if (group == Gicv3::G1NS && (ich_vmcr_el2 & ICH_VMCR_EL2_VCBPR))
{
- // reads return bpr0 + 1 saturated to 7, writes ignored
+ // bpr0 + 1 saturated to 7, WI
group = Gicv3::G0S;
sat_inc = true;
}
@@ -370,30 +383,34 @@
break;
}
+ // Interrupt Priority Mask Register
case MISCREG_ICC_PMR:
- case MISCREG_ICC_PMR_EL1: // Priority Mask Register
- if ((currEL() == EL1) && !inSecureState() &&
- (hcr_imo || hcr_fmo)) {
+ case MISCREG_ICC_PMR_EL1:
+ if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo))
{
return isa->readMiscRegNoEffect(MISCREG_ICV_PMR_EL1);
}
if (haveEL(EL3) && !inSecureState() &&
- (isa->readMiscRegNoEffect(MISCREG_SCR_EL3) & (1U << 2))) {
- /* NS GIC access and Group 0 is inaccessible to NS */
+ (isa->readMiscRegNoEffect(MISCREG_SCR_EL3) & (1U << 2))) {
+ // Spec sectio 4.8.1
+ // For Non-secure access to ICC_PMR_EL1 when SCR_EL3.FIQ == 1:
if ((value & 0x80) == 0) {
- /* NS should not see priorities in the Secure half of the
- * range */
+ // If the current priority mask value is in the range of
+ // 0x00-0x7F a read access returns the value 0x00.
value = 0;
} else if (value != 0xff) {
- /* Non-idle priority: show the Non-secure view of it */
+ // If the current priority mask value is in the range of
+ // 0x80-0xFF a read access returns the Non-secure read of
the
+ // current value.
value = (value << 1) & 0xff;
}
}
break;
+ // Interrupt Acknowledge Register 0
case MISCREG_ICC_IAR0:
- case MISCREG_ICC_IAR0_EL1: { // Interrupt Acknowledge Register 0
+ case MISCREG_ICC_IAR0_EL1: {
if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
return readMiscReg(MISCREG_ICV_IAR0_EL1);
}
@@ -415,6 +432,7 @@
break;
}
+ // Virtual Interrupt Acknowledge Register 0
case MISCREG_ICV_IAR0_EL1: {
int lr_idx = getHPPVILR();
uint32_t int_id = Gicv3::INTID_SPURIOUS;
@@ -427,7 +445,7 @@
int_id = value = bits(lr, 31, 0);
if (int_id < Gicv3::INTID_SECURE ||
- int_id > Gicv3::INTID_SPURIOUS) {
+ int_id > Gicv3::INTID_SPURIOUS) {
virtualActivateIRQ(lr_idx);
} else {
// Bogus... Pseudocode says:
@@ -435,7 +453,7 @@
// - Return de bogus id...
lr &= ~ICH_LR_EL2_STATE_PENDING_BIT;
isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx,
- lr);
+ lr);
}
}
}
@@ -445,8 +463,9 @@
break;
}
+ // Interrupt Acknowledge Register 1
case MISCREG_ICC_IAR1:
- case MISCREG_ICC_IAR1_EL1: { // Interrupt Acknowledge Register 1
+ case MISCREG_ICC_IAR1_EL1: {
if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
return readMiscReg(MISCREG_ICV_IAR1_EL1);
}
@@ -468,6 +487,7 @@
break;
}
+ // Virtual Interrupt Acknowledge Register 1
case MISCREG_ICV_IAR1_EL1: {
int lr_idx = getHPPVILR();
uint32_t int_id = Gicv3::INTID_SPURIOUS;
@@ -480,7 +500,7 @@
int_id = value = bits(lr, 31, 0);
if (int_id < Gicv3::INTID_SECURE ||
- int_id > Gicv3::INTID_SPURIOUS) {
+ int_id > Gicv3::INTID_SPURIOUS) {
virtualActivateIRQ(lr_idx);
} else {
// Bogus... Pseudocode says:
@@ -488,7 +508,7 @@
// - Return de bogus id...
lr &= ~ICH_LR_EL2_STATE_PENDING_BIT;
isa->setMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx,
- lr);
+ lr);
}
}
}
@@ -498,8 +518,9 @@
break;
}
+ // System Register Enable Register
case MISCREG_ICC_SRE:
- case MISCREG_ICC_SRE_EL1: { // System Register Enable Register
+ case MISCREG_ICC_SRE_EL1: {
bool dfb;
bool dib;
@@ -542,8 +563,9 @@
break;
}
+ // System Register Enable Register
case MISCREG_ICC_HSRE:
- case MISCREG_ICC_SRE_EL2: // System Register Enable Register
+ case MISCREG_ICC_SRE_EL2:
/*
* Enable [3] == 1
* (Secure EL1 accesses to Secure ICC_SRE_EL1 do not trap to EL2,
@@ -553,11 +575,12 @@
* SRE [0] == 1 (Only system register interface supported, RAO/WI)
*/
value = ICC_SRE_EL2_ENABLE | ICC_SRE_EL2_DIB | ICC_SRE_EL2_DFB |
- ICC_SRE_EL2_SRE;
+ ICC_SRE_EL2_SRE;
break;
+ // System Register Enable Register
case MISCREG_ICC_MSRE:
- case MISCREG_ICC_SRE_EL3: // System Register Enable Register
+ case MISCREG_ICC_SRE_EL3:
/*
* Enable [3] == 1
* (Secure EL1 accesses to Secure ICC_SRE_EL1 do not trap to EL3,
@@ -567,24 +590,25 @@
* SRE [0] == 1 (Only system register interface supported, RAO/WI)
*/
value = ICC_SRE_EL3_ENABLE | ICC_SRE_EL3_DIB | ICC_SRE_EL3_DFB |
- ICC_SRE_EL3_SRE;
+ ICC_SRE_EL3_SRE;
break;
+ // Control Register
case MISCREG_ICC_CTLR:
- case MISCREG_ICC_CTLR_EL1: { // Control Register
- if ((currEL() == EL1) && !inSecureState() &&
- (hcr_imo || hcr_fmo)) {
+ case MISCREG_ICC_CTLR_EL1: {
+ if ((currEL() == EL1) && !inSecureState() && (hcr_imo ||
hcr_fmo)) {
return readMiscReg(MISCREG_ICV_CTLR_EL1);
}
// Add value for RO bits
// IDbits [13:11], 001 = 24 bits | 000 = 16 bits
// PRIbits [10:8], number of priority bits implemented, minus one
- value |= ICC_CTLR_EL1_RSS | ICC_CTLR_EL1_A3V |
- (1 << 11) | ((PRIORITY_BITS - 1) << 8);
+ value |= ICC_CTLR_EL1_RSS | ICC_CTLR_EL1_A3V | (1 << 11) |
+ ((PRIORITY_BITS - 1) << 8);
break;
}
+ // Virtual Control Register
case MISCREG_ICV_CTLR_EL1: {
value = ICC_CTLR_EL1_A3V | (1 << ICC_CTLR_EL1_IDBITS_SHIFT) |
(7 << ICC_CTLR_EL1_PRIBITS_SHIFT);
@@ -602,6 +626,7 @@
break;
}
+ // Control Register
case MISCREG_ICC_MCTLR:
case MISCREG_ICC_CTLR_EL3: {
// Add value for RO bits
@@ -636,22 +661,25 @@
break;
}
+ // Hyp Control Register
case MISCREG_ICH_HCR:
case MISCREG_ICH_HCR_EL2:
break;
+ // Hyp Active Priorities Group 0 Registers
case MISCREG_ICH_AP0R0:
case MISCREG_ICH_AP0R0_EL2:
break;
+ // Hyp Active Priorities Group 1 Registers
case MISCREG_ICH_AP1R0:
case MISCREG_ICH_AP1R0_EL2:
break;
+ // Maintenance Interrupt State Register
case MISCREG_ICH_MISR:
case MISCREG_ICH_MISR_EL2: {
value = 0;
- // Scan list registers and fill in the U, NP and EOI bits
eoiMaintenanceInterruptStatus((uint32_t *) &value);
RegVal ich_hcr_el2 =
isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
@@ -659,33 +687,34 @@
isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
if (ich_hcr_el2 &
- (ICH_HCR_EL2_LRENPIE | ICH_HCR_EL2_EOICOUNT_MASK)) {
+ (ICH_HCR_EL2_LRENPIE | ICH_HCR_EL2_EOICOUNT_MASK)) {
value |= ICH_MISR_EL2_LRENP;
}
if ((ich_hcr_el2 & ICH_HCR_EL2_VGRP0EIE) &&
- (ich_vmcr_el2 & ICH_VMCR_EL2_VENG0)) {
+ (ich_vmcr_el2 & ICH_VMCR_EL2_VENG0)) {
value |= ICH_MISR_EL2_VGRP0E;
}
if ((ich_hcr_el2 & ICH_HCR_EL2_VGRP0DIE) &&
- !(ich_vmcr_el2 & ICH_VMCR_EL2_VENG1)) {
+ !(ich_vmcr_el2 & ICH_VMCR_EL2_VENG1)) {
value |= ICH_MISR_EL2_VGRP0D;
}
if ((ich_hcr_el2 & ICH_HCR_EL2_VGRP1EIE) &&
- (ich_vmcr_el2 & ICH_VMCR_EL2_VENG1)) {
+ (ich_vmcr_el2 & ICH_VMCR_EL2_VENG1)) {
value |= ICH_MISR_EL2_VGRP1E;
}
if ((ich_hcr_el2 & ICH_HCR_EL2_VGRP1DIE) &&
- !(ich_vmcr_el2 & ICH_VMCR_EL2_VENG1)) {
+ !(ich_vmcr_el2 & ICH_VMCR_EL2_VENG1)) {
value |= ICH_MISR_EL2_VGRP1D;
}
break;
}
+ // VGIC Type Register
case MISCREG_ICH_VTR:
case MISCREG_ICH_VTR_EL2:
/*
@@ -700,9 +729,7 @@
* TDS [19] == 0 (Implementation supports ICH_HCR_EL2.TDIR)
* ListRegs [4:0]
*/
- value = (16 - 1) << 0 |
- (5 - 1) << 26 |
- (5 - 1) << 29;
+ value = (16 - 1) << 0 | (5 - 1) << 26 | (5 - 1) << 29;
value =
((VIRTUAL_NUM_LIST_REGS - 1) << ICH_VTR_EL2_LISTREGS_SHIFT) |
// ICH_VTR_EL2_TDS |
@@ -713,11 +740,13 @@
((VIRTUAL_PRIORITY_BITS - 1) << ICH_VTR_EL2_PRIBITS_SHIFT);
break;
+ // End of Interrupt Status Registe
case MISCREG_ICH_EISR:
case MISCREG_ICH_EISR_EL2:
value = eoiMaintenanceInterruptStatus(nullptr);
break;
+ // Empty List Register Status Register
case MISCREG_ICH_ELRSR:
case MISCREG_ICH_ELRSR_EL2:
value = 0;
@@ -727,39 +756,42 @@
isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
if ((lr & ICH_LR_EL2_STATE_MASK) == 0 &&
- ((lr & ICH_LR_EL2_HW) != 0 ||
- (lr & ICH_LR_EL2_EOI) == 0)) {
+ ((lr & ICH_LR_EL2_HW) != 0 ||
+ (lr & ICH_LR_EL2_EOI) == 0)) {
value |= (1 << lr_idx);
}
}
break;
+ // List Registers
case MISCREG_ICH_LRC0 ... MISCREG_ICH_LRC15:
// AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 high half part)
value = value >> 32;
break;
+ // List Registers
case MISCREG_ICH_LR0 ... MISCREG_ICH_LR15:
// AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 low half part)
value = value & 0xffffffff;
break;
+ // List Registers
case MISCREG_ICH_LR0_EL2 ... MISCREG_ICH_LR15_EL2:
break;
+ // Virtual Machine Control Register
case MISCREG_ICH_VMCR:
case MISCREG_ICH_VMCR_EL2:
break;
default:
- panic("Gicv3CPUInterface::readMiscReg(): "
- "unknown register %d (%s)",
- misc_reg, miscRegName[misc_reg]);
+ panic("Gicv3CPUInterface::readMiscReg(): unknown register %d (%s)",
+ misc_reg, miscRegName[misc_reg]);
}
- DPRINTF(GIC, "Gicv3CPUInterface::readMiscReg(): "
- "register %s value %#x\n", miscRegName[misc_reg], value);
+ DPRINTF(GIC, "Gicv3CPUInterface::readMiscReg(): register %s
value %#x\n",
+ miscRegName[misc_reg], value);
return value;
}
@@ -767,12 +799,13 @@
Gicv3CPUInterface::setMiscReg(int misc_reg, RegVal val)
{
bool do_virtual_update = false;
- DPRINTF(GIC, "Gicv3CPUInterface::setMiscReg(): "
- "register %s value %#x\n", miscRegName[misc_reg], val);
+ DPRINTF(GIC, "Gicv3CPUInterface::setMiscReg(): register %s
value %#x\n",
+ miscRegName[misc_reg], val);
bool hcr_fmo = getHCREL2FMO();
bool hcr_imo = getHCREL2IMO();
switch (misc_reg) {
+ // Active Priorities Group 1 Registers
case MISCREG_ICC_AP1R0:
case MISCREG_ICC_AP1R0_EL1:
if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
@@ -783,17 +816,18 @@
case MISCREG_ICC_AP1R1:
case MISCREG_ICC_AP1R1_EL1:
-
// only implemented if supporting 6 or more bits of priority
+
case MISCREG_ICC_AP1R2:
case MISCREG_ICC_AP1R2_EL1:
-
// only implemented if supporting 7 or more bits of priority
+
case MISCREG_ICC_AP1R3:
case MISCREG_ICC_AP1R3_EL1:
// only implemented if supporting 7 or more bits of priority
break;
+ // Active Priorities Group 0 Registers
case MISCREG_ICC_AP0R0:
case MISCREG_ICC_AP0R0_EL1:
if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
@@ -804,17 +838,18 @@
case MISCREG_ICC_AP0R1:
case MISCREG_ICC_AP0R1_EL1:
-
// only implemented if supporting 6 or more bits of priority
+
case MISCREG_ICC_AP0R2:
case MISCREG_ICC_AP0R2_EL1:
-
// only implemented if supporting 7 or more bits of priority
+
case MISCREG_ICC_AP0R3:
case MISCREG_ICC_AP0R3_EL1:
// only implemented if supporting 7 or more bits of priority
break;
+ // End Of Interrupt Register 0
case MISCREG_ICC_EOIR0:
case MISCREG_ICC_EOIR0_EL1: { // End Of Interrupt Register 0
if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
@@ -843,6 +878,7 @@
break;
}
+ // Virtual End Of Interrupt Register 0
case MISCREG_ICV_EOIR0_EL1: {
int int_id = val & 0xffffff;
@@ -871,7 +907,7 @@
uint8_t lr_group_prio = bits(lr, 55, 48) & 0xf8;
if (lr_group == Gicv3::G0S && lr_group_prio == drop_prio) {
- //JAIRO if (!virtualIsEOISplitMode())
+ //if (!virtualIsEOISplitMode())
{
virtualDeactivateIRQ(lr_idx);
}
@@ -882,8 +918,9 @@
break;
}
+ // End Of Interrupt Register 1
case MISCREG_ICC_EOIR1:
- case MISCREG_ICC_EOIR1_EL1: { // End Of Interrupt Register 1
+ case MISCREG_ICC_EOIR1_EL1: {
if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
return setMiscReg(MISCREG_ICV_EOIR1_EL1, val);
}
@@ -895,8 +932,7 @@
return;
}
- Gicv3::GroupId group =
- inSecureState() ? Gicv3::G1S : Gicv3::G1NS;
+ Gicv3::GroupId group = inSecureState() ? Gicv3::G1S :
Gicv3::G1NS;
if (highestActiveGroup() == Gicv3::G0S) {
return;
@@ -906,7 +942,7 @@
if (highestActiveGroup() == Gicv3::G1S && !inSecureState()) {
return;
} else if (highestActiveGroup() == Gicv3::G1NS &&
- !(!inSecureState() or (currEL() == EL3))) {
+ !(!inSecureState() or (currEL() == EL3))) {
return;
}
}
@@ -920,12 +956,13 @@
break;
}
+ // Virtual End Of Interrupt Register 1
case MISCREG_ICV_EOIR1_EL1: {
int int_id = val & 0xffffff;
// avoid deactivation for special interrupts
if (int_id >= Gicv3::INTID_SECURE &&
- int_id <= Gicv3::INTID_SPURIOUS) {
+ int_id <= Gicv3::INTID_SPURIOUS) {
return;
}
@@ -938,7 +975,7 @@
int lr_idx = virtualFindActive(int_id);
if (lr_idx < 0) {
- // No LR found matching
+ // No matching LR found
virtualIncrementEOICount();
} else {
RegVal lr =
@@ -958,28 +995,29 @@
break;
}
+ // Deactivate Interrupt Register
case MISCREG_ICC_DIR:
- case MISCREG_ICC_DIR_EL1: { // Deactivate Interrupt Register
+ case MISCREG_ICC_DIR_EL1: {
if ((currEL() == EL1) && !inSecureState() &&
- (hcr_imo || hcr_fmo)) {
+ (hcr_imo || hcr_fmo)) {
return setMiscReg(MISCREG_ICV_DIR_EL1, val);
}
int int_id = val & 0xffffff;
- // avoid deactivation for special interrupts
+ // The following checks are as per spec pseudocode
+ // aarch64/support/ICC_DIR_EL1
+
+ // Check for spurious ID
if (int_id >= Gicv3::INTID_SECURE) {
return;
}
+ // EOI mode is not set, so don't deactivate
if (!isEOISplitMode()) {
return;
}
- /*
- * Check whether we're allowed to deactivate.
- * These checks are correspond to the spec's pseudocode.
- */
Gicv3::GroupId group =
int_id >= 32 ? distributor->getIntGroup(int_id) :
redistributor->getIntGroup(int_id);
@@ -1010,12 +1048,12 @@
case EL1:
if (!isSecureBelowEL3()) {
if (single_sec_state && irq_is_grp0 &&
- !route_fiq_to_el3 && !route_fiq_to_el2) {
+ !route_fiq_to_el3 && !route_fiq_to_el2) {
break;
}
if (!irq_is_secure && !irq_is_grp0 &&
- !route_irq_to_el3 && !route_irq_to_el2) {
+ !route_irq_to_el3 && !route_irq_to_el2) {
break;
}
} else {
@@ -1024,8 +1062,8 @@
}
if (!irq_is_grp0 &&
- (!irq_is_secure || !single_sec_state) &&
- !route_irq_to_el3) {
+ (!irq_is_secure || !single_sec_state) &&
+ !route_irq_to_el3) {
break;
}
}
@@ -1040,12 +1078,13 @@
break;
}
+ // Deactivate Virtual Interrupt Register
case MISCREG_ICV_DIR_EL1: {
int int_id = val & 0xffffff;
// avoid deactivation for special interrupts
if (int_id >= Gicv3::INTID_SECURE &&
- int_id <= Gicv3::INTID_SPURIOUS) {
+ int_id <= Gicv3::INTID_SPURIOUS) {
return;
}
@@ -1056,7 +1095,7 @@
int lr_idx = virtualFindActive(int_id);
if (lr_idx < 0) {
- // No LR found matching
+ // No matching LR found
virtualIncrementEOICount();
} else {
virtualDeactivateIRQ(lr_idx);
@@ -1066,10 +1105,12 @@
break;
}
+ // Binary Point Register 0
case MISCREG_ICC_BPR0:
- case MISCREG_ICC_BPR0_EL1: // Binary Point Register 0
+ case MISCREG_ICC_BPR0_EL1:
+ // Binary Point Register 1
case MISCREG_ICC_BPR1:
- case MISCREG_ICC_BPR1_EL1: { // Binary Point Register 1
+ case MISCREG_ICC_BPR1_EL1: {
if ((currEL() == EL1) && !inSecureState()) {
if (misc_reg == MISCREG_ICC_BPR0_EL1 && hcr_fmo) {
return setMiscReg(MISCREG_ICV_BPR0_EL1, val);
@@ -1085,18 +1126,16 @@
group = Gicv3::G1NS;
}
- if ((group == Gicv3::G1S) &&
- !isEL3OrMon() &&
- (isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S) &
- ICC_CTLR_EL1_CBPR)) {
+ if ((group == Gicv3::G1S) && !isEL3OrMon() &&
+ (isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S) &
+ ICC_CTLR_EL1_CBPR)) {
group = Gicv3::G0S;
}
- if ((group == Gicv3::G1NS) &&
- (currEL() < EL3) &&
- (isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS) &
- ICC_CTLR_EL1_CBPR)) {
- // Reads return BPR0 + 1 saturated to 7, WI
+ if ((group == Gicv3::G1NS) && (currEL() < EL3) &&
+ (isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS) &
+ ICC_CTLR_EL1_CBPR)) {
+ // BPR0 + 1 saturated to 7, WI
return;
}
@@ -1111,7 +1150,9 @@
break;
}
+ // Virtual Binary Point Register 0
case MISCREG_ICV_BPR0_EL1:
+ // Virtual Binary Point Register 1
case MISCREG_ICV_BPR1_EL1: {
Gicv3::GroupId group =
misc_reg == MISCREG_ICV_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1NS;
@@ -1119,7 +1160,7 @@
isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
if (group == Gicv3::G1NS && (ich_vmcr_el2 & ICH_VMCR_EL2_VCBPR))
{
- // reads return bpr0 + 1 saturated to 7, writes ignored
+ // BPR0 + 1 saturated to 7, WI
return;
}
@@ -1135,12 +1176,14 @@
if (group == Gicv3::G0S) {
ich_vmcr_el2 = insertBits(ich_vmcr_el2,
- ICH_VMCR_EL2_VBPR0_SHIFT + 2,
ICH_VMCR_EL2_VBPR0_SHIFT,
- val);
+ ICH_VMCR_EL2_VBPR0_SHIFT + 2,
+ ICH_VMCR_EL2_VBPR0_SHIFT,
+ val);
} else {
ich_vmcr_el2 = insertBits(ich_vmcr_el2,
- ICH_VMCR_EL2_VBPR1_SHIFT + 2,
ICH_VMCR_EL2_VBPR1_SHIFT,
- val);
+ ICH_VMCR_EL2_VBPR1_SHIFT + 2,
+ ICH_VMCR_EL2_VBPR1_SHIFT,
+ val);
}
isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
@@ -1148,10 +1191,10 @@
break;
}
+ // Control Register
case MISCREG_ICC_CTLR:
- case MISCREG_ICC_CTLR_EL1: { // Control Register
- if ((currEL() == EL1) && !inSecureState() &&
- (hcr_imo || hcr_fmo)) {
+ case MISCREG_ICC_CTLR_EL1: {
+ if ((currEL() == EL1) && !inSecureState() && (hcr_imo ||
hcr_fmo)) {
return setMiscReg(MISCREG_ICV_CTLR_EL1, val);
}
@@ -1183,18 +1226,20 @@
break;
}
+ // Virtual Control Register
case MISCREG_ICV_CTLR_EL1: {
RegVal ich_vmcr_el2 =
isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
ich_vmcr_el2 = insertBits(ich_vmcr_el2, ICH_VMCR_EL2_VCBPR_SHIFT,
- val & ICC_CTLR_EL1_CBPR ? 1 : 0);
+ val & ICC_CTLR_EL1_CBPR ? 1 : 0);
ich_vmcr_el2 = insertBits(ich_vmcr_el2, ICH_VMCR_EL2_VEOIM_SHIFT,
- val & ICC_CTLR_EL1_EOIMODE ? 1 : 0);
+ val & ICC_CTLR_EL1_EOIMODE ? 1 : 0);
isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
do_virtual_update = true;
break;
}
+ // Control Register
case MISCREG_ICC_MCTLR:
case MISCREG_ICC_CTLR_EL3: {
RegVal icc_ctlr_el1_s =
@@ -1242,10 +1287,10 @@
break;
}
+ // Priority Mask Register
case MISCREG_ICC_PMR:
- case MISCREG_ICC_PMR_EL1: { // Priority Mask Register
- if ((currEL() == EL1) && !inSecureState() &&
- (hcr_imo || hcr_fmo)) {
+ case MISCREG_ICC_PMR_EL1: {
+ if ((currEL() == EL1) && !inSecureState() && (hcr_imo ||
hcr_fmo)) {
return isa->setMiscRegNoEffect(MISCREG_ICV_PMR_EL1, val);
}
@@ -1253,19 +1298,22 @@
SCR scr_el3 = isa->readMiscRegNoEffect(MISCREG_SCR_EL3);
if (haveEL(EL3) && !inSecureState() && (scr_el3.fiq)) {
- /*
- * NS access and Group 0 is inaccessible to NS: return the
- * NS view of the current priority
- */
+ // Spec section 4.8.1
+ // For Non-secure access to ICC_PMR_EL1 SCR_EL3.FIQ == 1:
RegVal old_icc_pmr_el1 =
isa->readMiscRegNoEffect(MISCREG_ICC_PMR_EL1);
if (!(old_icc_pmr_el1 & 0x80)) {
- /* Current PMR in the secure range, don't allow NS to
- * change it */
+ // If the current priority mask value is in the range of
+ // 0x00-0x7F then WI
return;
}
+ // If the current priority mask value is in the range of
+ // 0x80-0xFF then a write access to ICC_PMR_EL1 succeeds,
+ // based on the Non-secure read of the priority mask value
+ // written to the register.
+
val = (val >> 1) | 0x80;
}
@@ -1273,8 +1321,9 @@
break;
}
+ // Interrupt Group 0 Enable Register
case MISCREG_ICC_IGRPEN0:
- case MISCREG_ICC_IGRPEN0_EL1: { // Interrupt Group 0 Enable Register
+ case MISCREG_ICC_IGRPEN0_EL1: {
if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
return setMiscReg(MISCREG_ICV_IGRPEN0_EL1, val);
}
@@ -1282,17 +1331,19 @@
break;
}
+ // Virtual Interrupt Group 0 Enable register
case MISCREG_ICV_IGRPEN0_EL1: {
bool enable = val & 0x1;
RegVal ich_vmcr_el2 =
isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
ich_vmcr_el2 = insertBits(ich_vmcr_el2,
- ICH_VMCR_EL2_VENG0_SHIFT, enable);
+ ICH_VMCR_EL2_VENG0_SHIFT, enable);
isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
virtualUpdate();
return;
}
+ // Interrupt Group 1 Enable register
case MISCREG_ICC_IGRPEN1:
case MISCREG_ICC_IGRPEN1_EL1: { // Interrupt Group 1 Enable Register
if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
@@ -1302,17 +1353,19 @@
break;
}
+ // Virtual Interrupt Group 1 Enable register
case MISCREG_ICV_IGRPEN1_EL1: {
bool enable = val & 0x1;
RegVal ich_vmcr_el2 =
isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
ich_vmcr_el2 = insertBits(ich_vmcr_el2,
- ICH_VMCR_EL2_VENG1_SHIFT, enable);
+ ICH_VMCR_EL2_VENG1_SHIFT, enable);
isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
virtualUpdate();
return;
}
+ // Interrupt Group 1 Enable register
case MISCREG_ICC_MGRPEN1:
case MISCREG_ICC_IGRPEN1_EL3: {
// EnableGrp1S and EnableGrp1NS are aliased with
@@ -1324,15 +1377,15 @@
return;
}
- // Software Generated Interrupt Group 0 Register
+ // Software Generated Interrupt Group 0 Register
case MISCREG_ICC_SGI0R:
case MISCREG_ICC_SGI0R_EL1:
- // Software Generated Interrupt Group 1 Register
+ // Software Generated Interrupt Group 1 Register
case MISCREG_ICC_SGI1R:
case MISCREG_ICC_SGI1R_EL1:
- // Alias Software Generated Interrupt Group 1 Register
+ // Alias Software Generated Interrupt Group 1 Register
case MISCREG_ICC_ASGI1R:
case MISCREG_ICC_ASGI1R_EL1: {
bool ns = !inSecureState();
@@ -1373,14 +1426,14 @@
// Interrupts routed to the PEs specified by
// Aff3.Aff2.Aff1.<target list>
if ((affinity_i >> 8) !=
- ((aff3 << 16) | (aff2 << 8) | (aff1 << 0))) {
+ ((aff3 << 16) | (aff2 << 8) | (aff1 << 0))) {
continue;
}
uint8_t aff0_i = bits(affinity_i, 7, 0);
if (!(aff0_i >= rs * 16 && aff0_i < (rs + 1) * 16 &&
- ((0x1 << (aff0_i - rs * 16)) &
target_list))) {
+ ((0x1 << (aff0_i - rs * 16)) & target_list))) {
continue;
}
}
@@ -1391,11 +1444,12 @@
break;
}
+ // System Register Enable Register EL1
case MISCREG_ICC_SRE:
- case MISCREG_ICC_SRE_EL1: { // System Register Enable Register EL1
+ case MISCREG_ICC_SRE_EL1: {
if (!(val & ICC_SRE_EL1_SRE)) {
warn("Gicv3CPUInterface::setMiscReg(): "
- "ICC_SRE_EL*.SRE is RAO/WI, legacy not
supported!\n");
+ "ICC_SRE_EL*.SRE is RAO/WI, legacy not supported!\n");
}
bool dfb = val & ICC_SRE_EL1_DFB;
@@ -1422,18 +1476,21 @@
return;
}
+ // System Register Enable Register EL2
case MISCREG_ICC_HSRE:
- case MISCREG_ICC_SRE_EL2: // System Register Enable Register EL2
+ case MISCREG_ICC_SRE_EL2:
+ // System Register Enable Register EL3
case MISCREG_ICC_MSRE:
- case MISCREG_ICC_SRE_EL3: // System Register Enable Register EL3
+ case MISCREG_ICC_SRE_EL3:
if (!(val & (1 << 0))) {
warn("Gicv3CPUInterface::setMiscReg(): "
- "ICC_SRE_EL*.SRE is RAO/WI, legacy not supported!\n");
+ "ICC_SRE_EL*.SRE is RAO/WI, legacy not supported!\n");
}
// All bits are RAO/WI
break;
+ // Hyp Control Register
case MISCREG_ICH_HCR:
case MISCREG_ICH_HCR_EL2:
val &= ICH_HCR_EL2_EN | ICH_HCR_EL2_UIE | ICH_HCR_EL2_LRENPIE |
@@ -1445,18 +1502,20 @@
do_virtual_update = true;
break;
+ // List Registers
case MISCREG_ICH_LRC0 ... MISCREG_ICH_LRC15:
// AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 high half part)
{
- // Enforce RES0 bits in priority field, 5 of 8 bits used
+ // RES0 bits in priority field, 5 of 8 bits used
val = insertBits(val, ICH_LRC_PRIORITY_SHIFT + 2,
- ICH_LRC_PRIORITY_SHIFT, 0);
+ ICH_LRC_PRIORITY_SHIFT, 0);
RegVal old_val = isa->readMiscRegNoEffect(misc_reg);
val = (old_val & 0xffffffff) | (val << 32);
do_virtual_update = true;
break;
}
+ // List Registers
case MISCREG_ICH_LR0 ... MISCREG_ICH_LR15: {
// AArch32 (maps to AArch64 MISCREG_ICH_LR<n>_EL2 low half part)
RegVal old_val = isa->readMiscRegNoEffect(misc_reg);
@@ -1465,14 +1524,16 @@
break;
}
+ // List Registers
case MISCREG_ICH_LR0_EL2 ... MISCREG_ICH_LR15_EL2: { // AArch64
- // Enforce RES0 bits in priority field, 5 of 8 bits used
+ // RES0 bits in priority field, 5 of 8 bits used
val = insertBits(val, ICH_LR_EL2_PRIORITY_SHIFT + 2,
- ICH_LR_EL2_PRIORITY_SHIFT, 0);
+ ICH_LR_EL2_PRIORITY_SHIFT, 0);
do_virtual_update = true;
break;
}
+ // Virtual Machine Control Register
case MISCREG_ICH_VMCR:
case MISCREG_ICH_VMCR_EL2: {
val &= ICH_VMCR_EL2_VENG0 | ICH_VMCR_EL2_VENG1 |
@@ -1488,22 +1549,23 @@
vbpr0 = vbpr0 < min_vpr0 ? min_vpr0 : vbpr0;
vbpr1 = vbpr1 < min_vpr1 ? min_vpr1 : vbpr1;
val = insertBits(val, ICH_VMCR_EL2_VBPR0_SHIFT + 2,
- ICH_VMCR_EL2_VBPR0_SHIFT, vbpr0);
+ ICH_VMCR_EL2_VBPR0_SHIFT, vbpr0);
val = insertBits(val, ICH_VMCR_EL2_VBPR1_SHIFT + 2,
- ICH_VMCR_EL2_VBPR1_SHIFT, vbpr1);
+ ICH_VMCR_EL2_VBPR1_SHIFT, vbpr1);
break;
}
+ // Hyp Active Priorities Group 0 Registers
case MISCREG_ICH_AP0R0 ... MISCREG_ICH_AP0R3:
case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_AP0R3_EL2:
+ // Hyp Active Priorities Group 1 Registers
case MISCREG_ICH_AP1R0 ... MISCREG_ICH_AP1R3:
case MISCREG_ICH_AP1R0_EL2 ... MISCREG_ICH_AP1R3_EL2:
break;
default:
- panic("Gicv3CPUInterface::setMiscReg(): "
- "unknown register %d (%s)",
- misc_reg, miscRegName[misc_reg]);
+ panic("Gicv3CPUInterface::setMiscReg(): unknown register %d (%s)",
+ misc_reg, miscRegName[misc_reg]);
}
isa->setMiscRegNoEffect(misc_reg, val);
@@ -1514,7 +1576,7 @@
}
int
-Gicv3CPUInterface::virtualFindActive(uint32_t int_id)
+Gicv3CPUInterface::virtualFindActive(uint32_t int_id) const
{
for (uint32_t lr_idx = 0; lr_idx < VIRTUAL_NUM_LIST_REGS; lr_idx++) {
RegVal lr =
@@ -1530,7 +1592,7 @@
}
uint32_t
-Gicv3CPUInterface::getHPPIR0()
+Gicv3CPUInterface::getHPPIR0() const
{
if (hppi.prio == 0xff) {
return Gicv3::INTID_SPURIOUS;
@@ -1539,9 +1601,7 @@
bool irq_is_secure = !distributor->DS && hppi.group != Gicv3::G1NS;
if ((hppi.group != Gicv3::G0S) && isEL3OrMon()) {
- /* Indicate to EL3 that there's a Group 1 interrupt for the
- * other state pending.
- */
+ // interrupt for the other state pending
return irq_is_secure ? Gicv3::INTID_SECURE :
Gicv3::INTID_NONSECURE;
}
@@ -1558,7 +1618,7 @@
}
uint32_t
-Gicv3CPUInterface::getHPPIR1()
+Gicv3CPUInterface::getHPPIR1() const
{
if (hppi.prio == 0xff) {
return Gicv3::INTID_SPURIOUS;
@@ -1566,7 +1626,7 @@
//if ((currEL() == EL3) && ICC_CTLR_EL3_RM)
if ((currEL() == EL3) &&
- isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3) &
ICC_CTLR_EL3_RM) {
+ isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3) & ICC_CTLR_EL3_RM) {
if (hppi.group == Gicv3::G0S) {
return Gicv3::INTID_SECURE;
} else if (hppi.group == Gicv3::G1NS) {
@@ -1603,7 +1663,6 @@
apr = isa->readMiscRegNoEffect(apr_misc_reg);
if (apr) {
- /* Clear the lowest set bit */
apr &= apr - 1;
isa->setMiscRegNoEffect(apr_misc_reg, apr);
}
@@ -1614,14 +1673,6 @@
uint8_t
Gicv3CPUInterface::virtualDropPriority()
{
- /* Drop the priority of the currently active virtual interrupt
- * (favouring group 0 if there is a set active bit at
- * the same priority for both group 0 and group 1).
- * Return the priority value for the bit we just cleared,
- * or 0xff if no bits were set in the AP registers at all.
- * Note that though the ich_apr[] are uint64_t only the low
- * 32 bits are actually relevant.
- */
int apr_max = 1 << (VIRTUAL_PREEMPTION_BITS - 5);
for (int i = 0; i < apr_max; i++) {
@@ -1636,12 +1687,10 @@
int vapr1_count = ctz32(vapr1);
if (vapr0_count <= vapr1_count) {
- /* Clear the lowest set bit */
vapr0 &= vapr0 - 1;
isa->setMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i, vapr0);
return (vapr0_count + i * 32) << (GIC_MIN_VBPR + 1);
} else {
- /* Clear the lowest set bit */
vapr1 &= vapr1 - 1;
isa->setMiscRegNoEffect(MISCREG_ICH_AP1R0_EL2 + i, vapr1);
return (vapr1_count + i * 32) << (GIC_MIN_VBPR + 1);
@@ -1738,34 +1787,18 @@
}
/*
- * Return a mask word which clears the subpriority bits from
- * a priority value for an interrupt in the specified group.
- * This depends on the BPR value. For CBPR0 (S or NS):
- * a BPR of 0 means the group priority bits are [7:1];
- * a BPR of 1 means they are [7:2], and so on down to
- * ...
- * a BPR of 7 meaning no group priority bits at all.
- * For CBPR1 NS:
- * a BPR of 0 is impossible (the minimum value is 1)
- * a BPR of 1 means the group priority bits are [7:1];
- * a BPR of 2 means they are [7:2], and so on down to
- * ...
- * a BPR of 7 meaning the group priority is [7].
- *
- * Which BPR to use depends on the group of the interrupt and
- * the current ICC_CTLR.CBPR settings.
- *
- * This corresponds to the GroupBits() pseudocode from 4.8.2.
+ * Returns the priority group field for the current BPR value for the
group.
+ * GroupBits() Pseudocode from spec.
*/
uint32_t
-Gicv3CPUInterface::groupPriorityMask(Gicv3::GroupId group)
+Gicv3CPUInterface::groupPriorityMask(Gicv3::GroupId group) const
{
if ((group == Gicv3::G1S &&
- isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S)
- & ICC_CTLR_EL1_CBPR) ||
- (group == Gicv3::G1NS &&
- isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS)
- & ICC_CTLR_EL1_CBPR)) {
+ isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S)
+ & ICC_CTLR_EL1_CBPR) ||
+ (group == Gicv3::G1NS &&
+ isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS)
+ & ICC_CTLR_EL1_CBPR)) {
group = Gicv3::G0S;
}
@@ -1786,7 +1819,7 @@
}
uint32_t
-Gicv3CPUInterface::virtualGroupPriorityMask(Gicv3::GroupId group)
+Gicv3CPUInterface::virtualGroupPriorityMask(Gicv3::GroupId group) const
{
RegVal ich_vmcr_el2 =
isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
@@ -1812,7 +1845,7 @@
}
bool
-Gicv3CPUInterface::isEOISplitMode()
+Gicv3CPUInterface::isEOISplitMode() const
{
if (isEL3OrMon()) {
return isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3) &
@@ -1824,14 +1857,14 @@
}
bool
-Gicv3CPUInterface::virtualIsEOISplitMode()
+Gicv3CPUInterface::virtualIsEOISplitMode() const
{
RegVal ich_vmcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
return ich_vmcr_el2 & ICH_VMCR_EL2_VEOIM;
}
int
-Gicv3CPUInterface::highestActiveGroup()
+Gicv3CPUInterface::highestActiveGroup() const
{
int g0_ctz = ctz32(isa->readMiscRegNoEffect(MISCREG_ICC_AP0R0_EL1));
int gq_ctz = ctz32(isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_S));
@@ -1933,7 +1966,7 @@
// Returns the intex of the LR with the HPPI
int
-Gicv3CPUInterface::getHPPVILR()
+Gicv3CPUInterface::getHPPVILR() const
{
int idx = -1;
RegVal ich_vmcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
@@ -1978,7 +2011,7 @@
}
bool
-Gicv3CPUInterface::hppviCanPreempt(int lr_idx)
+Gicv3CPUInterface::hppviCanPreempt(int lr_idx) const
{
RegVal lr = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
@@ -2013,7 +2046,7 @@
}
uint8_t
-Gicv3CPUInterface::virtualHighestActivePriority()
+Gicv3CPUInterface::virtualHighestActivePriority() const
{
uint8_t num_aprs = 1 << (VIRTUAL_PRIORITY_BITS - 5);
@@ -2044,12 +2077,9 @@
isa->setMiscRegNoEffect(MISCREG_ICH_HCR_EL2, ich_hcr_el2);
}
-/*
- * Should we signal the interrupt as IRQ or FIQ?
- * see spec section 4.6.2
- */
+// spec section 4.6.2
ArmISA::InterruptTypes
-Gicv3CPUInterface::intSignalType(Gicv3::GroupId group)
+Gicv3CPUInterface::intSignalType(Gicv3::GroupId group) const
{
bool is_fiq = false;
@@ -2079,7 +2109,7 @@
}
bool
-Gicv3CPUInterface::hppiCanPreempt()
+Gicv3CPUInterface::hppiCanPreempt() const
{
if (hppi.prio == 0xff) {
// there is no pending interrupt
@@ -2112,7 +2142,7 @@
}
uint8_t
-Gicv3CPUInterface::highestActivePriority()
+Gicv3CPUInterface::highestActivePriority() const
{
uint32_t apr = isa->readMiscRegNoEffect(MISCREG_ICC_AP0R0_EL1) |
isa->readMiscRegNoEffect(MISCREG_ICC_AP1R0_EL1_NS) |
@@ -2127,7 +2157,7 @@
}
bool
-Gicv3CPUInterface::groupEnabled(Gicv3::GroupId group)
+Gicv3CPUInterface::groupEnabled(Gicv3::GroupId group) const
{
switch (group) {
case Gicv3::G0S:
@@ -2157,7 +2187,7 @@
}
bool
-Gicv3CPUInterface::inSecureState()
+Gicv3CPUInterface::inSecureState() const
{
if (!gic->getSystem()->haveSecurity()) {
return false;
@@ -2169,7 +2199,7 @@
}
int
-Gicv3CPUInterface::currEL()
+Gicv3CPUInterface::currEL() const
{
CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);
bool is_64 = opModeIs64((OperatingMode)(uint8_t) cpsr.mode);
@@ -2194,7 +2224,7 @@
}
bool
-Gicv3CPUInterface::haveEL(ExceptionLevel el)
+Gicv3CPUInterface::haveEL(ExceptionLevel el) const
{
switch (el) {
case EL0:
@@ -2214,21 +2244,21 @@
}
bool
-Gicv3CPUInterface::isSecureBelowEL3()
+Gicv3CPUInterface::isSecureBelowEL3() const
{
SCR scr = isa->readMiscRegNoEffect(MISCREG_SCR_EL3);
return haveEL(EL3) && scr.ns == 0;
}
bool
-Gicv3CPUInterface::isAA64()
+Gicv3CPUInterface::isAA64() const
{
CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);
return opModeIs64((OperatingMode)(uint8_t) cpsr.mode);
}
bool
-Gicv3CPUInterface::isEL3OrMon()
+Gicv3CPUInterface::isEL3OrMon() const
{
if (haveEL(EL3)) {
CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);
@@ -2245,15 +2275,8 @@
}
uint32_t
-Gicv3CPUInterface::eoiMaintenanceInterruptStatus(uint32_t * misr)
+Gicv3CPUInterface::eoiMaintenanceInterruptStatus(uint32_t * misr) const
{
- /* Return a set of bits indicating the EOI maintenance interrupt status
- * for each list register. The EOI maintenance interrupt status is
- * 1 if LR.State == 0 && LR.HW == 0 && LR.EOI == 1
- * (see the GICv3 spec for the ICH_EISR_EL2 register).
- * If misr is not NULL then we should also collect the information
- * about the MISR.EOI, MISR.NP and MISR.U bits.
- */
uint32_t value = 0;
int valid_count = 0;
bool seen_pending = false;
@@ -2262,7 +2285,7 @@
RegVal lr = isa->readMiscRegNoEffect(MISCREG_ICH_LR0_EL2 + lr_idx);
if ((lr & (ICH_LR_EL2_STATE_MASK | ICH_LR_EL2_HW |
ICH_LR_EL2_EOI)) ==
- ICH_LR_EL2_EOI) {
+ ICH_LR_EL2_EOI) {
value |= (1 << lr_idx);
}
@@ -2297,13 +2320,9 @@
}
uint32_t
-Gicv3CPUInterface::maintenanceInterruptStatus()
+Gicv3CPUInterface::maintenanceInterruptStatus() const
{
- /* Return a set of bits indicating the maintenance interrupt status
- * (as seen in the ICH_MISR_EL2 register).
- */
uint32_t value = 0;
- /* Scan list registers and fill in the U, NP and EOI bits */
eoiMaintenanceInterruptStatus(&value);
RegVal ich_hcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
RegVal ich_vmcr_el2 = isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
@@ -2313,22 +2332,22 @@
}
if ((ich_hcr_el2 & ICH_HCR_EL2_VGRP0EIE) &&
- (ich_vmcr_el2 & ICH_VMCR_EL2_VENG0)) {
+ (ich_vmcr_el2 & ICH_VMCR_EL2_VENG0)) {
value |= ICH_MISR_EL2_VGRP0E;
}
if ((ich_hcr_el2 & ICH_HCR_EL2_VGRP0DIE) &&
- !(ich_vmcr_el2 & ICH_VMCR_EL2_VENG1)) {
+ !(ich_vmcr_el2 & ICH_VMCR_EL2_VENG1)) {
value |= ICH_MISR_EL2_VGRP0D;
}
if ((ich_hcr_el2 & ICH_HCR_EL2_VGRP1EIE) &&
- (ich_vmcr_el2 & ICH_VMCR_EL2_VENG1)) {
+ (ich_vmcr_el2 & ICH_VMCR_EL2_VENG1)) {
value |= ICH_MISR_EL2_VGRP1E;
}
if ((ich_hcr_el2 & ICH_HCR_EL2_VGRP1DIE) &&
- !(ich_vmcr_el2 & ICH_VMCR_EL2_VENG1)) {
+ !(ich_vmcr_el2 & ICH_VMCR_EL2_VENG1)) {
value |= ICH_MISR_EL2_VGRP1D;
}
diff --git a/src/dev/arm/gic_v3_cpu_interface.hh
b/src/dev/arm/gic_v3_cpu_interface.hh
index 3752f55..3705305 100644
--- a/src/dev/arm/gic_v3_cpu_interface.hh
+++ b/src/dev/arm/gic_v3_cpu_interface.hh
@@ -34,15 +34,15 @@
#include "arch/arm/isa_device.hh"
#include "dev/arm/gic_v3.hh"
-class Gicv3Redistributor;
class Gicv3Distributor;
+class Gicv3Redistributor;
class Gicv3CPUInterface : public ArmISA::BaseISADevice, public Serializable
{
private:
- friend class Gicv3Redistributor;
friend class Gicv3Distributor;
+ friend class Gicv3Redistributor;
protected:
@@ -55,57 +55,57 @@
static const uint32_t ICC_SRE_EL1_DFB = 1 << 1;
static const uint32_t ICC_SRE_EL1_DIB = 1 << 2;
- static const uint32_t ICC_SRE_EL2_SRE = 1 << 0;
- static const uint32_t ICC_SRE_EL2_DFB = 1 << 1;
- static const uint32_t ICC_SRE_EL2_DIB = 1 << 2;
+ static const uint32_t ICC_SRE_EL2_SRE = 1 << 0;
+ static const uint32_t ICC_SRE_EL2_DFB = 1 << 1;
+ static const uint32_t ICC_SRE_EL2_DIB = 1 << 2;
static const uint32_t ICC_SRE_EL2_ENABLE = 1 << 3;
- static const uint32_t ICC_SRE_EL3_SRE = 1 << 0;
- static const uint32_t ICC_SRE_EL3_DFB = 1 << 1;
- static const uint32_t ICC_SRE_EL3_DIB = 1 << 2;
+ static const uint32_t ICC_SRE_EL3_SRE = 1 << 0;
+ static const uint32_t ICC_SRE_EL3_DFB = 1 << 1;
+ static const uint32_t ICC_SRE_EL3_DIB = 1 << 2;
static const uint32_t ICC_SRE_EL3_ENABLE = 1 << 3;
- static const uint32_t ICC_CTLR_EL3_CBPR_EL1S = 1 << 0;
- static const uint32_t ICC_CTLR_EL3_CBPR_EL1NS = 1 << 1;
- static const uint32_t ICC_CTLR_EL3_EOIMODE_EL3 = 1 << 2;
- static const uint32_t ICC_CTLR_EL3_EOIMODE_EL1S = 1 << 3;
+ static const uint32_t ICC_CTLR_EL3_CBPR_EL1S = 1 << 0;
+ static const uint32_t ICC_CTLR_EL3_CBPR_EL1NS = 1 << 1;
+ static const uint32_t ICC_CTLR_EL3_EOIMODE_EL3 = 1 << 2;
+ static const uint32_t ICC_CTLR_EL3_EOIMODE_EL1S = 1 << 3;
static const uint32_t ICC_CTLR_EL3_EOIMODE_EL1NS = 1 << 4;
- static const uint32_t ICC_CTLR_EL3_RM = 1 << 5;
- static const uint32_t ICC_CTLR_EL3_PMHE = 1 << 6;
+ static const uint32_t ICC_CTLR_EL3_RM = 1 << 5;
+ static const uint32_t ICC_CTLR_EL3_PMHE = 1 << 6;
+ static const uint32_t ICC_CTLR_EL3_SEIS = 1 << 14;
+ static const uint32_t ICC_CTLR_EL3_A3V = 1 << 15;
+ static const uint32_t ICC_CTLR_EL3_nDS = 1 << 17;
+ static const uint32_t ICC_CTLR_EL3_RSS = 1 << 18;
static const uint32_t ICC_CTLR_EL3_PRIBITS_SHIFT = 8;
- static const uint32_t ICC_CTLR_EL3_IDBITS_SHIFT = 11;
- static const uint32_t ICC_CTLR_EL3_SEIS = 1 << 14;
- static const uint32_t ICC_CTLR_EL3_A3V = 1 << 15;
- static const uint32_t ICC_CTLR_EL3_nDS = 1 << 17;
- static const uint32_t ICC_CTLR_EL3_RSS = 1 << 18;
+ static const uint32_t ICC_CTLR_EL3_IDBITS_SHIFT = 11;
- static const uint32_t ICC_CTLR_EL1_CBPR = 1 << 0;
- static const uint32_t ICC_CTLR_EL1_EOIMODE = 1 << 1;
- static const uint32_t ICC_CTLR_EL1_PMHE = 1 << 6;
- static const uint32_t ICC_CTLR_EL1_SEIS = 1 << 14;
- static const uint32_t ICC_CTLR_EL1_A3V = 1 << 15;
- static const uint32_t ICC_CTLR_EL1_RSS = 1 << 18;
+ static const uint32_t ICC_CTLR_EL1_CBPR = 1 << 0;
+ static const uint32_t ICC_CTLR_EL1_EOIMODE = 1 << 1;
+ static const uint32_t ICC_CTLR_EL1_PMHE = 1 << 6;
+ static const uint32_t ICC_CTLR_EL1_SEIS = 1 << 14;
+ static const uint32_t ICC_CTLR_EL1_A3V = 1 << 15;
+ static const uint32_t ICC_CTLR_EL1_RSS = 1 << 18;
static const uint32_t ICC_CTLR_EL1_PRIBITS_SHIFT = 8;
- static const uint32_t ICC_CTLR_EL1_PRIBITS_MASK =
+ static const uint32_t ICC_CTLR_EL1_IDBITS_SHIFT = 11;
+ static const uint32_t ICC_CTLR_EL1_PRIBITS_MASK =
7U << ICC_CTLR_EL1_PRIBITS_SHIFT;
- static const uint32_t ICC_CTLR_EL1_IDBITS_SHIFT = 11;
static const uint32_t ICC_IGRPEN0_EL1_ENABLE = 1 << 0;
static const uint32_t ICC_IGRPEN1_EL1_ENABLE = 1 << 0;
static const uint32_t ICC_IGRPEN1_EL3_ENABLEGRP1NS = 1 << 0;
- static const uint32_t ICC_IGRPEN1_EL3_ENABLEGRP1S = 1 << 1;
+ static const uint32_t ICC_IGRPEN1_EL3_ENABLEGRP1S = 1 << 1;
static const uint8_t PRIORITY_BITS = 5;
- /* Minimum BPR for Secure, or when security not enabled */
+ // Minimum BPR for Secure, or when security not enabled
static const uint8_t GIC_MIN_BPR = 2;
- /* Minimum BPR for Nonsecure when security is enabled */
+ // Minimum BPR for Nonsecure when security is enabled
static const uint8_t GIC_MIN_BPR_NS = GIC_MIN_BPR + 1;
- static const uint8_t VIRTUAL_PRIORITY_BITS = 5;
+ static const uint8_t VIRTUAL_PRIORITY_BITS = 5;
static const uint8_t VIRTUAL_PREEMPTION_BITS = 5;
- static const uint8_t VIRTUAL_NUM_LIST_REGS = 16;
+ static const uint8_t VIRTUAL_NUM_LIST_REGS = 16;
static const uint8_t GIC_MIN_VBPR = 7 - VIRTUAL_PREEMPTION_BITS;
@@ -119,19 +119,19 @@
// GIC CPU interface memory mapped control registers (legacy)
enum {
- GICC_CTLR = 0x0000,
- GICC_PMR = 0x0004,
- GICC_BPR = 0x0008,
- GICC_IAR = 0x000C,
- GICC_EOIR = 0x0010,
- GICC_RPR = 0x0014,
- GICC_HPPI = 0x0018,
- GICC_ABPR = 0x001C,
- GICC_AIAR = 0x0020,
- GICC_AEOIR = 0x0024,
- GICC_AHPPIR = 0x0028,
+ GICC_CTLR = 0x0000,
+ GICC_PMR = 0x0004,
+ GICC_BPR = 0x0008,
+ GICC_IAR = 0x000C,
+ GICC_EOIR = 0x0010,
+ GICC_RPR = 0x0014,
+ GICC_HPPI = 0x0018,
+ GICC_ABPR = 0x001C,
+ GICC_AIAR = 0x0020,
+ GICC_AEOIR = 0x0024,
+ GICC_AHPPIR = 0x0028,
GICC_STATUSR = 0x002C,
- GICC_IIDR = 0x00FC,
+ GICC_IIDR = 0x00FC,
};
static const AddrRange GICC_APR;
@@ -139,163 +139,158 @@
// GIC CPU virtual interface memory mapped control registers (legacy)
enum {
- GICH_HCR = 0x0000,
- GICH_VTR = 0x0004,
- GICH_VMCR = 0x0008,
- GICH_MISR = 0x0010,
- GICH_EISR = 0x0020,
+ GICH_HCR = 0x0000,
+ GICH_VTR = 0x0004,
+ GICH_VMCR = 0x0008,
+ GICH_MISR = 0x0010,
+ GICH_EISR = 0x0020,
GICH_ELRSR = 0x0030,
};
static const AddrRange GICH_APR;
static const AddrRange GICH_LR;
- static const uint32_t ICH_HCR_EL2_EN = 1 << 0;
- static const uint32_t ICH_HCR_EL2_UIE = 1 << 1;
- static const uint32_t ICH_HCR_EL2_LRENPIE = 1 << 2;
- static const uint32_t ICH_HCR_EL2_NPIE = 1 << 3;
- static const uint32_t ICH_HCR_EL2_VGRP0EIE = 1 << 4;
- static const uint32_t ICH_HCR_EL2_VGRP0DIE = 1 << 5;
- static const uint32_t ICH_HCR_EL2_VGRP1EIE = 1 << 6;
- static const uint32_t ICH_HCR_EL2_VGRP1DIE = 1 << 7;
- static const uint32_t ICH_HCR_EL2_TC = 1 << 10;
- static const uint32_t ICH_HCR_EL2_TALL0 = 1 << 11;
- static const uint32_t ICH_HCR_EL2_TALL1 = 1 << 12;
- static const uint32_t ICH_HCR_EL2_TSEI = 1 << 13;
- static const uint32_t ICH_HCR_EL2_TDIR = 1 << 14;
- static const uint32_t ICH_HCR_EL2_EOICOUNT_MASK = 0x1fU << 27;
+ static const uint32_t ICH_HCR_EL2_EN = 1 << 0;
+ static const uint32_t ICH_HCR_EL2_UIE = 1 << 1;
+ static const uint32_t ICH_HCR_EL2_LRENPIE = 1 << 2;
+ static const uint32_t ICH_HCR_EL2_NPIE = 1 << 3;
+ static const uint32_t ICH_HCR_EL2_VGRP0EIE = 1 << 4;
+ static const uint32_t ICH_HCR_EL2_VGRP0DIE = 1 << 5;
+ static const uint32_t ICH_HCR_EL2_VGRP1EIE = 1 << 6;
+ static const uint32_t ICH_HCR_EL2_VGRP1DIE = 1 << 7;
+ static const uint32_t ICH_HCR_EL2_TC = 1 << 10;
+ static const uint32_t ICH_HCR_EL2_TALL0 = 1 << 11;
+ static const uint32_t ICH_HCR_EL2_TALL1 = 1 << 12;
+ static const uint32_t ICH_HCR_EL2_TSEI = 1 << 13;
+ static const uint32_t ICH_HCR_EL2_TDIR = 1 << 14;
+ static const uint32_t ICH_HCR_EL2_EOICOUNT_MASK = 0x1f << 27;
- static const uint64_t ICH_LR_EL2_VINTID_SHIFT = 0;
- static const uint64_t ICH_LR_EL2_VINTID_LENGTH = 32;
- static const uint64_t ICH_LR_EL2_VINTID_MASK =
- (0xffffffffULL << ICH_LR_EL2_VINTID_SHIFT);
- static const uint64_t ICH_LR_EL2_PINTID_SHIFT = 32;
- static const uint64_t ICH_LR_EL2_PINTID_LENGTH = 10;
- static const uint64_t ICH_LR_EL2_PINTID_MASK =
- (0x3ffULL << ICH_LR_EL2_PINTID_SHIFT);
- /* Note that EOI shares with the top bit of the pINTID field */
- static const uint64_t ICH_LR_EL2_EOI = (1ULL << 41);
- static const uint64_t ICH_LR_EL2_PRIORITY_SHIFT = 48;
- static const uint64_t ICH_LR_EL2_PRIORITY_LENGTH = 8;
- static const uint64_t ICH_LR_EL2_PRIORITY_MASK =
- (0xffULL << ICH_LR_EL2_PRIORITY_SHIFT);
- static const uint64_t ICH_LR_EL2_GROUP = (1ULL << 60);
- static const uint64_t ICH_LR_EL2_HW = (1ULL << 61);
- static const uint64_t ICH_LR_EL2_STATE_SHIFT = 62;
- static const uint64_t ICH_LR_EL2_STATE_LENGTH = 2;
- static const uint64_t ICH_LR_EL2_STATE_MASK =
- (3ULL << ICH_LR_EL2_STATE_SHIFT);
- /* values for the state field: */
- static const uint64_t ICH_LR_EL2_STATE_INVALID = 0;
- static const uint64_t ICH_LR_EL2_STATE_PENDING = 1;
- static const uint64_t ICH_LR_EL2_STATE_ACTIVE = 2;
+ static const uint64_t ICH_LR_EL2_VINTID_SHIFT = 0;
+ static const uint64_t ICH_LR_EL2_PINTID_SHIFT = 32;
+ static const uint64_t ICH_LR_EL2_PRIORITY_SHIFT = 48;
+ static const uint64_t ICH_LR_EL2_STATE_SHIFT = 62;
+ static const uint64_t ICH_LR_EL2_VINTID_LENGTH = 32;
+ static const uint64_t ICH_LR_EL2_PINTID_LENGTH = 10;
+ static const uint64_t ICH_LR_EL2_PRIORITY_LENGTH = 8;
+ static const uint64_t ICH_LR_EL2_STATE_LENGTH = 2;
+ static const uint64_t ICH_LR_EL2_VINTID_MASK =
+ 0xffffffff << ICH_LR_EL2_VINTID_SHIFT;
+ static const uint64_t ICH_LR_EL2_PINTID_MASK =
+ 0x3ffULL << ICH_LR_EL2_PINTID_SHIFT;
+ static const uint64_t ICH_LR_EL2_PRIORITY_MASK =
+ 0xffULL << ICH_LR_EL2_PRIORITY_SHIFT;
+ static const uint64_t ICH_LR_EL2_STATE_MASK =
+ 0x3ULL << ICH_LR_EL2_STATE_SHIFT;
+ static const uint64_t ICH_LR_EL2_EOI = 1ULL << 41;
+ static const uint64_t ICH_LR_EL2_GROUP = 1ULL << 60;
+ static const uint64_t ICH_LR_EL2_HW = 1ULL << 61;
+ static const uint64_t ICH_LR_EL2_STATE_INVALID = 0;
+ static const uint64_t ICH_LR_EL2_STATE_PENDING = 1;
+ static const uint64_t ICH_LR_EL2_STATE_ACTIVE = 2;
static const uint64_t ICH_LR_EL2_STATE_ACTIVE_PENDING = 3;
- static const uint64_t ICH_LR_EL2_STATE_PENDING_BIT =
- (1ULL << ICH_LR_EL2_STATE_SHIFT);
- static const uint64_t ICH_LR_EL2_STATE_ACTIVE_BIT =
- (2ULL << ICH_LR_EL2_STATE_SHIFT);
+ static const uint64_t ICH_LR_EL2_STATE_PENDING_BIT =
+ 0x1ULL << ICH_LR_EL2_STATE_SHIFT;
+ static const uint64_t ICH_LR_EL2_STATE_ACTIVE_BIT =
+ 0x2ULL << ICH_LR_EL2_STATE_SHIFT;
static const uint64_t ICH_LRC_PRIORITY_SHIFT =
ICH_LR_EL2_PRIORITY_SHIFT - 32;
static const uint64_t ICH_LRC_PRIORITY_LENGTH =
ICH_LR_EL2_PRIORITY_LENGTH;
- static const uint32_t ICH_MISR_EL2_EOI = (1 << 0);
- static const uint32_t ICH_MISR_EL2_U = (1 << 1);
- static const uint32_t ICH_MISR_EL2_LRENP = (1 << 2);
- static const uint32_t ICH_MISR_EL2_NP = (1 << 3);
- static const uint32_t ICH_MISR_EL2_VGRP0E = (1 << 4);
- static const uint32_t ICH_MISR_EL2_VGRP0D = (1 << 5);
- static const uint32_t ICH_MISR_EL2_VGRP1E = (1 << 6);
- static const uint32_t ICH_MISR_EL2_VGRP1D = (1 << 7);
+ static const uint32_t ICH_MISR_EL2_EOI = 1 << 0;
+ static const uint32_t ICH_MISR_EL2_U = 1 << 1;
+ static const uint32_t ICH_MISR_EL2_LRENP = 1 << 2;
+ static const uint32_t ICH_MISR_EL2_NP = 1 << 3;
+ static const uint32_t ICH_MISR_EL2_VGRP0E = 1 << 4;
+ static const uint32_t ICH_MISR_EL2_VGRP0D = 1 << 5;
+ static const uint32_t ICH_MISR_EL2_VGRP1E = 1 << 6;
+ static const uint32_t ICH_MISR_EL2_VGRP1D = 1 << 7;
- static const uint32_t ICH_VMCR_EL2_VENG0_SHIFT = 0;
- static const uint32_t ICH_VMCR_EL2_VENG0 =
- (1 << ICH_VMCR_EL2_VENG0_SHIFT);
- static const uint32_t ICH_VMCR_EL2_VENG1_SHIFT = 1;
- static const uint32_t ICH_VMCR_EL2_VENG1 =
- (1 << ICH_VMCR_EL2_VENG1_SHIFT);
- static const uint32_t ICH_VMCR_EL2_VACKCTL = (1 << 2);
- static const uint32_t ICH_VMCR_EL2_VFIQEN = (1 << 3);
- static const uint32_t ICH_VMCR_EL2_VCBPR_SHIFT = 4;
- static const uint32_t ICH_VMCR_EL2_VCBPR =
- (1 << ICH_VMCR_EL2_VCBPR_SHIFT);
- static const uint32_t ICH_VMCR_EL2_VEOIM_SHIFT = 9;
- static const uint32_t ICH_VMCR_EL2_VEOIM =
- (1 << ICH_VMCR_EL2_VEOIM_SHIFT);
- static const uint32_t ICH_VMCR_EL2_VBPR1_SHIFT = 18;
+ static const uint32_t ICH_VMCR_EL2_VENG0_SHIFT = 0;
+ static const uint32_t ICH_VMCR_EL2_VENG1_SHIFT = 1;
+ static const uint32_t ICH_VMCR_EL2_VCBPR_SHIFT = 4;
+ static const uint32_t ICH_VMCR_EL2_VEOIM_SHIFT = 9;
+ static const uint32_t ICH_VMCR_EL2_VBPR1_SHIFT = 18;
+ static const uint32_t ICH_VMCR_EL2_VBPR0_SHIFT = 21;
+ static const uint32_t ICH_VMCR_EL2_VPMR_SHIFT = 24;
static const uint32_t ICH_VMCR_EL2_VBPR1_LENGTH = 3;
- static const uint32_t ICH_VMCR_EL2_VBPR1_MASK =
- (0x7U << ICH_VMCR_EL2_VBPR1_SHIFT);
- static const uint32_t ICH_VMCR_EL2_VBPR0_SHIFT = 21;
static const uint32_t ICH_VMCR_EL2_VBPR0_LENGTH = 3;
- static const uint32_t ICH_VMCR_EL2_VBPR0_MASK =
- (0x7U << ICH_VMCR_EL2_VBPR0_SHIFT);
- static const uint32_t ICH_VMCR_EL2_VPMR_SHIFT = 24;
- static const uint32_t ICH_VMCR_EL2_VPMR_LENGTH = 8;
- static const uint32_t ICH_VMCR_EL2_VPMR_MASK =
- (0xffU << ICH_VMCR_EL2_VPMR_SHIFT);
+ static const uint32_t ICH_VMCR_EL2_VPMR_LENGTH = 8;
+ static const uint32_t ICH_VMCR_EL2_VENG0 =
+ 1 << ICH_VMCR_EL2_VENG0_SHIFT;
+ static const uint32_t ICH_VMCR_EL2_VENG1 =
+ 1 << ICH_VMCR_EL2_VENG1_SHIFT;
+ static const uint32_t ICH_VMCR_EL2_VACKCTL = 1 << 2;
+ static const uint32_t ICH_VMCR_EL2_VFIQEN = 1 << 3;
+ static const uint32_t ICH_VMCR_EL2_VCBPR =
+ 1 << ICH_VMCR_EL2_VCBPR_SHIFT;
+ static const uint32_t ICH_VMCR_EL2_VEOIM =
+ 1 << ICH_VMCR_EL2_VEOIM_SHIFT;
+ static const uint32_t ICH_VMCR_EL2_VBPR1_MASK =
+ 0x7 << ICH_VMCR_EL2_VBPR1_SHIFT;
+ static const uint32_t ICH_VMCR_EL2_VBPR0_MASK =
+ 0x7 << ICH_VMCR_EL2_VBPR0_SHIFT;
+ static const uint32_t ICH_VMCR_EL2_VPMR_MASK =
+ 0xff << ICH_VMCR_EL2_VPMR_SHIFT;
static const uint32_t ICH_VTR_EL2_LISTREGS_SHIFT = 0;
- static const uint32_t ICH_VTR_EL2_TDS = 1 << 19;
- static const uint32_t ICH_VTR_EL2_NV4 = 1 << 20;
- static const uint32_t ICH_VTR_EL2_A3V = 1 << 21;
- static const uint32_t ICH_VTR_EL2_SEIS = 1 << 22;
- static const uint32_t ICH_VTR_EL2_IDBITS_SHIFT = 23;
- static const uint32_t ICH_VTR_EL2_PREBITS_SHIFT = 26;
- static const uint32_t ICH_VTR_EL2_PRIBITS_SHIFT = 29;
+ static const uint32_t ICH_VTR_EL2_IDBITS_SHIFT = 23;
+ static const uint32_t ICH_VTR_EL2_PREBITS_SHIFT = 26;
+ static const uint32_t ICH_VTR_EL2_PRIBITS_SHIFT = 29;
+ static const uint32_t ICH_VTR_EL2_TDS = 1 << 19;
+ static const uint32_t ICH_VTR_EL2_NV4 = 1 << 20;
+ static const uint32_t ICH_VTR_EL2_A3V = 1 << 21;
+ static const uint32_t ICH_VTR_EL2_SEIS = 1 << 22;
+
+ protected:
+
+ void activateIRQ(uint32_t intid, Gicv3::GroupId group);
+ int currEL() const;
+ void deactivateIRQ(uint32_t intid, Gicv3::GroupId group);
+ void dropPriority(Gicv3::GroupId group);
+ uint32_t eoiMaintenanceInterruptStatus(uint32_t * misr) const;
+ bool getHCREL2FMO() const;
+ bool getHCREL2IMO() const;
+ uint32_t getHPPIR0() const;
+ uint32_t getHPPIR1() const;
+ int getHPPVILR() const;
+ bool groupEnabled(Gicv3::GroupId group) const;
+ uint32_t groupPriorityMask(Gicv3::GroupId group) const;
+ bool haveEL(ArmISA::ExceptionLevel el) const;
+ int highestActiveGroup() const;
+ uint8_t highestActivePriority() const;
+ bool hppiCanPreempt() const;
+ bool hppviCanPreempt(int lrIdx) const;
+ bool inSecureState() const;
+ ArmISA::InterruptTypes intSignalType(Gicv3::GroupId group) const;
+ bool isAA64() const;
+ bool isEL3OrMon() const;
+ bool isEOISplitMode() const;
+ bool isSecureBelowEL3() const;
+ uint32_t maintenanceInterruptStatus() const;
+ RegVal readMiscReg(int misc_reg) override;
+ void reset();
+ void serialize(CheckpointOut & cp) const override;
+ void setMiscReg(int misc_reg, RegVal val) override;
+ void unserialize(CheckpointIn & cp) override;
+ void update();
+ void virtualActivateIRQ(uint32_t lrIdx);
+ void virtualDeactivateIRQ(int lrIdx);
+ uint8_t virtualDropPriority();
+ int virtualFindActive(uint32_t intid) const;
+ uint32_t virtualGroupPriorityMask(Gicv3::GroupId group) const;
+ uint8_t virtualHighestActivePriority() const;
+ void virtualIncrementEOICount();
+ bool virtualIsEOISplitMode() const;
+ void virtualUpdate();
public:
Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id);
- ~Gicv3CPUInterface();
+
void init();
void initState();
-
- RegVal readMiscReg(int misc_reg) override;
- void setMiscReg(int misc_reg, RegVal val) override;
- void update();
- void virtualUpdate();
-
- void serialize(CheckpointOut & cp) const override;
- void unserialize(CheckpointIn & cp) override;
-
- protected:
-
- void reset();
- bool hppiCanPreempt();
- bool hppviCanPreempt(int lrIdx);
- bool groupEnabled(Gicv3::GroupId group);
- uint8_t highestActivePriority();
- uint8_t virtualHighestActivePriority();
- bool inSecureState();
- int currEL();
- bool haveEL(ArmISA::ExceptionLevel el);
- void activateIRQ(uint32_t intid, Gicv3::GroupId group);
- void virtualActivateIRQ(uint32_t lrIdx);
- void deactivateIRQ(uint32_t intid, Gicv3::GroupId group);
- void virtualDeactivateIRQ(int lrIdx);
- uint32_t groupPriorityMask(Gicv3::GroupId group);
- uint32_t virtualGroupPriorityMask(Gicv3::GroupId group);
- void dropPriority(Gicv3::GroupId group);
- uint8_t virtualDropPriority();
- ArmISA::InterruptTypes intSignalType(Gicv3::GroupId group);
- bool isEOISplitMode();
- bool virtualIsEOISplitMode();
- bool isSecureBelowEL3();
- bool inSecureState2();
- uint32_t eoiMaintenanceInterruptStatus(uint32_t * misr);
- uint32_t maintenanceInterruptStatus();
- int highestActiveGroup();
- bool getHCREL2FMO();
- bool getHCREL2IMO();
- uint32_t getHPPIR1();
- uint32_t getHPPIR0();
- int getHPPVILR();
- int virtualFindActive(uint32_t intid);
- void virtualIncrementEOICount();
- bool isEL3OrMon();
- bool isAA64();
};
#endif //__DEV_ARM_GICV3_CPU_INTERFACE_H__
diff --git a/src/dev/arm/gic_v3_distributor.cc
b/src/dev/arm/gic_v3_distributor.cc
index 00f29a7..fd8ca75 100644
--- a/src/dev/arm/gic_v3_distributor.cc
+++ b/src/dev/arm/gic_v3_distributor.cc
@@ -27,6 +27,7 @@
*
* Authors: Jairo Balart
*/
+
#include "dev/arm/gic_v3_distributor.hh"
#include <algorithm>
@@ -36,21 +37,21 @@
#include "dev/arm/gic_v3_cpu_interface.hh"
#include "dev/arm/gic_v3_redistributor.hh"
-const AddrRange Gicv3Distributor::GICD_IGROUPR(0x0080, 0x00ff);
-const AddrRange Gicv3Distributor::GICD_ISENABLER(0x0100, 0x017f);
-const AddrRange Gicv3Distributor::GICD_ICENABLER(0x0180, 0x01ff);
-const AddrRange Gicv3Distributor::GICD_ISPENDR(0x0200, 0x027f);
-const AddrRange Gicv3Distributor::GICD_ICPENDR(0x0280, 0x02ff);
-const AddrRange Gicv3Distributor::GICD_ISACTIVER(0x0300, 0x037f);
-const AddrRange Gicv3Distributor::GICD_ICACTIVER(0x0380, 0x03ff);
+const AddrRange Gicv3Distributor::GICD_IGROUPR (0x0080, 0x00ff);
+const AddrRange Gicv3Distributor::GICD_ISENABLER (0x0100, 0x017f);
+const AddrRange Gicv3Distributor::GICD_ICENABLER (0x0180, 0x01ff);
+const AddrRange Gicv3Distributor::GICD_ISPENDR (0x0200, 0x027f);
+const AddrRange Gicv3Distributor::GICD_ICPENDR (0x0280, 0x02ff);
+const AddrRange Gicv3Distributor::GICD_ISACTIVER (0x0300, 0x037f);
+const AddrRange Gicv3Distributor::GICD_ICACTIVER (0x0380, 0x03ff);
const AddrRange Gicv3Distributor::GICD_IPRIORITYR(0x0400, 0x07ff);
-const AddrRange Gicv3Distributor::GICD_ITARGETSR(0x0800, 0x08ff);
-const AddrRange Gicv3Distributor::GICD_ICFGR(0x0c00, 0x0cff);
-const AddrRange Gicv3Distributor::GICD_IGRPMODR(0x0d00, 0x0d7f);
-const AddrRange Gicv3Distributor::GICD_NSACR(0x0e00, 0x0eff);
-const AddrRange Gicv3Distributor::GICD_CPENDSGIR(0x0f10, 0x0f1f);
-const AddrRange Gicv3Distributor::GICD_SPENDSGIR(0x0f20, 0x0f2f);
-const AddrRange Gicv3Distributor::GICD_IROUTER(0x6000, 0x7fe0);
+const AddrRange Gicv3Distributor::GICD_ITARGETSR (0x0800, 0x08ff);
+const AddrRange Gicv3Distributor::GICD_ICFGR (0x0c00, 0x0cff);
+const AddrRange Gicv3Distributor::GICD_IGRPMODR (0x0d00, 0x0d7f);
+const AddrRange Gicv3Distributor::GICD_NSACR (0x0e00, 0x0eff);
+const AddrRange Gicv3Distributor::GICD_CPENDSGIR (0x0f10, 0x0f1f);
+const AddrRange Gicv3Distributor::GICD_SPENDSGIR (0x0f20, 0x0f2f);
+const AddrRange Gicv3Distributor::GICD_IROUTER (0x6000, 0x7fe0);
Gicv3Distributor::Gicv3Distributor(Gicv3 * gic, uint32_t it_lines)
: gic(gic),
@@ -68,10 +69,6 @@
panic_if(it_lines > Gicv3::INTID_SECURE, "Invalid value for
it_lines!");
}
-Gicv3Distributor::~Gicv3Distributor()
-{
-}
-
void
Gicv3Distributor::init()
{
@@ -132,13 +129,13 @@
}
for (int i = 0, int_id = first_intid; i < 8 * size && int_id <
itLines;
- i++, int_id++) {
+ i++, int_id++) {
val |= irqGroup[int_id] << i;
}
return val;
- // Interrupt Set-Enable Registers
} else if (GICD_ISENABLER.contains(addr)) {
+ // Interrupt Set-Enable Registers
uint64_t val = 0x0;
int first_intid = (addr - GICD_ISENABLER.start()) * 8;
@@ -147,7 +144,8 @@
}
for (int i = 0, int_id = first_intid; i < 8 * size && int_id <
itLines;
- i++, int_id++) {
+ i++, int_id++) {
+
if (nsAccessToSecInt(int_id, is_secure_access))
{
continue;
@@ -167,7 +165,8 @@
}
for (int i = 0, int_id = first_intid; i < 8 * size && int_id <
itLines;
- i++, int_id++) {
+ i++, int_id++) {
+
if (nsAccessToSecInt(int_id, is_secure_access))
{
continue;
@@ -178,6 +177,7 @@
return val;
} else if (GICD_ISPENDR.contains(addr)) {
+ // Interrupt Set-Pending Registers
uint64_t val = 0x0;
int first_intid = (addr - GICD_ISPENDR.start()) * 8;
@@ -186,7 +186,8 @@
}
for (int i = 0, int_id = first_intid; i < 8 * size && int_id <
itLines;
- i++, int_id++) {
+ i++, int_id++) {
+
if (nsAccessToSecInt(int_id, is_secure_access))
{
if (irqNsacr[int_id] == 0) {
@@ -200,6 +201,7 @@
return val;
} else if (GICD_ICPENDR.contains(addr)) {
+ // Interrupt Clear-Pending Registers
uint64_t val = 0x0;
int first_intid = (addr - GICD_ICPENDR.start()) * 8;
@@ -208,7 +210,8 @@
}
for (int i = 0, int_id = first_intid; i < 8 * size && int_id <
itLines;
- i++, int_id++) {
+ i++, int_id++) {
+
if (nsAccessToSecInt(int_id, is_secure_access))
{
if (irqNsacr[int_id] < 2) {
@@ -221,8 +224,8 @@
}
return val;
- // Interrupt Set-Active Registers
} else if (GICD_ISACTIVER.contains(addr)) {
+ // Interrupt Set-Active Registers
int first_intid = (addr - GICD_ISACTIVER.start()) * 8;
if (isNotSPI(first_intid)) {
@@ -232,7 +235,8 @@
uint64_t val = 0x0;
for (int i = 0, int_id = first_intid; i < 8 * size && int_id <
itLines;
- i++, int_id++) {
+ i++, int_id++) {
+
if (nsAccessToSecInt(int_id, is_secure_access))
{
// Group 0 or Secure Group 1 interrupts are RAZ/WI
@@ -245,8 +249,8 @@
}
return val;
- // Interrupt Clear-Active Registers
} else if (GICD_ICACTIVER.contains(addr)) {
+ // Interrupt Clear-Active Registers
int first_intid = (addr - GICD_ICACTIVER.start()) * 8;
if (isNotSPI(first_intid)) {
@@ -256,7 +260,8 @@
uint64_t val = 0x0;
for (int i = 0, int_id = first_intid; i < 8 * size && int_id <
itLines;
- i++, int_id++) {
+ i++, int_id++) {
+
if (nsAccessToSecInt(int_id, is_secure_access))
{
if (irqNsacr[int_id] < 2) {
@@ -268,8 +273,8 @@
}
return val;
- // Interrupt Priority Registers
} else if (GICD_IPRIORITYR.contains(addr)) {
+ // Interrupt Priority Registers
uint64_t val = 0x0;
int first_intid = addr - GICD_IPRIORITYR.start();
@@ -278,7 +283,8 @@
}
for (int i = 0, int_id = first_intid; i < size && int_id < itLines;
- i++, int_id++) {
+ i++, int_id++) {
+
uint8_t prio = irqPriority[int_id];
if (!DS && !is_secure_access) {
@@ -301,8 +307,8 @@
warn("Gicv3Distributor::read(): "
"GICD_ITARGETSR is RAZ/WI, legacy not supported!\n");
return 0;
- // Interrupt Configuration Registers
} else if (GICD_ICFGR.contains(addr)) {
+ // Interrupt Configuration Registers
int first_intid = (addr - GICD_ICFGR.start()) * 4;
if (isNotSPI(first_intid)) {
@@ -312,7 +318,8 @@
uint64_t val = 0x0;
for (int i = 0, int_id = first_intid; i < 8 * size && int_id <
itLines;
- i = i + 2, int_id++) {
+ i = i + 2, int_id++) {
+
if (nsAccessToSecInt(int_id, is_secure_access))
{
continue;
@@ -343,16 +350,15 @@
uint64_t val = 0x0;
for (int i = 0, int_id = first_intid;
- i < 8 * size && int_id < itLines; i++, int_id++) {
+ i < 8 * size && int_id < itLines; i++, int_id++) {
val |= irqGrpmod[int_id] << i;
}
return val;
}
}
-
- // Non-secure Access Control Registers
} else if (GICD_NSACR.contains(addr)) {
+ // Non-secure Access Control Registers
// 2 bits per interrupt
int first_intid = (addr - GICD_NSACR.start()) * 4;
@@ -367,7 +373,7 @@
uint64_t val = 0x0;
for (int i = 0, int_id = first_intid;
- i < 8 * size && int_id < itLines; i = i + 2, int_id++) {
+ i < 8 * size && int_id < itLines; i = i + 2, int_id++) {
val |= irqNsacr[int_id] << i;
}
@@ -467,8 +473,8 @@
int max_spi_int_id = itLines - 1;
int it_lines_number = ceil((max_spi_int_id + 1) / 32.0) - 1;
return (1 << 26) | (1 << 25) | (1 << 24) | (0xf << 19) |
- (gic->getSystem()->haveSecurity() << 10) |
- (it_lines_number << 0);
+ (gic->getSystem()->haveSecurity() << 10) |
+ (it_lines_number << 0);
}
case GICD_IIDR: // Implementer Identification Register
@@ -479,10 +485,8 @@
// Optional register, RAZ/WI
return 0x0;
- case GICD_PIDR0: { // Peripheral ID0 Register
- uint8_t part_0 = 0x92; // Part number, bits[7:0]
- return part_0;
- }
+ case GICD_PIDR0: // Peripheral ID0 Register
+ return 0x92; // Part number, bits[7:0]
case GICD_PIDR1: { // Peripheral ID1 Register
uint8_t des_0 = 0xB; // JEP106 identification code, bits[3:0]
@@ -534,15 +538,15 @@
}
for (int i = 0, int_id = first_intid; i < 8 * size && int_id <
itLines;
- i++, int_id++) {
+ i++, int_id++) {
irqGroup[int_id] = data & (1 << i) ? 1 : 0;
DPRINTF(GIC, "Gicv3Distributor::write(): int_id %d group %d\n",
int_id, irqGroup[int_id]);
}
return;
- // Interrupt Set-Enable Registers
} else if (GICD_ISENABLER.contains(addr)) {
+ // Interrupt Set-Enable Registers
int first_intid = (addr - GICD_ISENABLER.start()) * 8;
if (isNotSPI(first_intid)) {
@@ -550,7 +554,8 @@
}
for (int i = 0, int_id = first_intid; i < 8 * size && int_id <
itLines;
- i++, int_id++) {
+ i++, int_id++) {
+
if (nsAccessToSecInt(int_id, is_secure_access))
{
continue;
@@ -574,7 +579,8 @@
int first_intid = (addr - GICD_ICENABLER.start()) * 8;
for (int i = 0, int_id = first_intid; i < 8 * size && int_id <
itLines;
- i++, int_id++) {
+ i++, int_id++) {
+
if (nsAccessToSecInt(int_id, is_secure_access))
{
continue;
@@ -594,6 +600,7 @@
return;
} else if (GICD_ISPENDR.contains(addr)) {
+ // Interrupt Set-Pending Registers
int first_intid = (addr - GICD_ISPENDR.start()) * 8;
if (isNotSPI(first_intid)) {
@@ -601,7 +608,8 @@
}
for (int i = 0, int_id = first_intid; i < 8 * size && int_id <
itLines;
- i++, int_id++) {
+ i++, int_id++) {
+
if (nsAccessToSecInt(int_id, is_secure_access))
{
if (irqNsacr[int_id] == 0) {
@@ -622,6 +630,7 @@
updateAndInformCPUInterfaces();
return;
} else if (GICD_ICPENDR.contains(addr)) {
+ // Interrupt Clear-Pending Registers
int first_intid = (addr - GICD_ICPENDR.start()) * 8;
if (isNotSPI(first_intid)) {
@@ -629,7 +638,8 @@
}
for (int i = 0, int_id = first_intid; i < 8 * size && int_id <
itLines;
- i++, int_id++) {
+ i++, int_id++) {
+
if (nsAccessToSecInt(int_id, is_secure_access))
{
if (irqNsacr[int_id] < 2) {
@@ -647,8 +657,8 @@
updateAndInformCPUInterfaces();
return;
- // Interrupt Set-Active Registers
} else if (GICD_ISACTIVER.contains(addr)) {
+ // Interrupt Set-Active Registers
int first_intid = (addr - GICD_ISACTIVER.start()) * 8;
if (isNotSPI(first_intid)) {
@@ -656,7 +666,8 @@
}
for (int i = 0, int_id = first_intid; i < 8 * size && int_id <
itLines;
- i++, int_id++) {
+ i++, int_id++) {
+
if (nsAccessToSecInt(int_id, is_secure_access))
{
continue;
@@ -679,7 +690,8 @@
}
for (int i = 0, int_id = first_intid; i < 8 * size && int_id <
itLines;
- i++, int_id++) {
+ i++, int_id++) {
+
if (nsAccessToSecInt(int_id, is_secure_access))
{
continue;
@@ -698,8 +710,8 @@
}
return;
- // Interrupt Priority Registers
} else if (GICD_IPRIORITYR.contains(addr)) {
+ // Interrupt Priority Registers
int first_intid = addr - GICD_IPRIORITYR.start();
if (isNotSPI(first_intid)) {
@@ -731,9 +743,13 @@
warn("Gicv3Distributor::write(): "
"GICD_ITARGETSR is RAZ/WI, legacy not supported!\n");
return;
- // Interrupt Configuration Registers
} else if (GICD_ICFGR.contains(addr)) {
- /* Here only the odd bits are used; even bits are RES0 */
+ // Interrupt Configuration Registers
+ // for x = 0 to 15:
+ // GICD_ICFGR[2x] = RES0
+ // GICD_ICFGR[2x + 1] =
+ // 0 level-sensitive
+ // 1 edge-triggered
int first_intid = (addr - GICD_ICFGR.start()) * 4;
if (isNotSPI(first_intid)) {
@@ -741,7 +757,7 @@
}
for (int i = 0, int_id = first_intid; i < 8 * size && int_id <
itLines;
- i = i + 2, int_id++) {
+ i = i + 2, int_id++) {
irqConfig[int_id] = data & (0x2 << i) ?
Gicv3::INT_EDGE_TRIGGERED :
Gicv3::INT_LEVEL_SENSITIVE;
@@ -766,7 +782,7 @@
}
for (int i = 0, int_id = first_intid;
- i < 8 * size && int_id < itLines; i++, int_id++) {
+ i < 8 * size && int_id < itLines; i++, int_id++) {
irqGrpmod[int_id] = data & (0x1 << i);
}
@@ -774,8 +790,8 @@
}
}
- // Non-secure Access Control Registers
} else if (GICD_NSACR.contains(addr)) {
+ // Non-secure Access Control Registers
// 2 bits per interrupt
int first_intid = (addr - GICD_NSACR.start()) * 4;
@@ -788,7 +804,7 @@
}
for (int i = 0, int_id = first_intid;
- i < 8 * size && int_id < itLines; i = i + 2, int_id++) {
+ i < 8 * size && int_id < itLines; i = i + 2, int_id++) {
irqNsacr[int_id] = (data >> (2 * int_id)) & 0x3;
}
@@ -924,7 +940,7 @@
}
void
-Gicv3Distributor::intDeasserted(uint32_t int_id)
+Gicv3Distributor::deassertSPI(uint32_t int_id)
{
panic_if(int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX, "Invalid SPI!");
panic_if(int_id > itLines, "Invalid SPI!");
@@ -965,12 +981,12 @@
// Find the highest priority pending SPI
for (int int_id = Gicv3::SGI_MAX + Gicv3::PPI_MAX; int_id < itLines;
- int_id++) {
+ int_id++) {
Gicv3::GroupId int_group = getIntGroup(int_id);
bool group_enabled = groupEnabled(int_group);
if (irqPending[int_id] && irqEnabled[int_id] &&
- !irqActive[int_id] && group_enabled) {
+ !irqActive[int_id] && group_enabled) {
IROUTER affinity_routing = irqAffinityRouting[int_id];
Gicv3Redistributor * target_redistributor = nullptr;
@@ -1005,13 +1021,13 @@
uint32_t target_cpu = target_redistributor->cpuId;
if ((irqPriority[int_id] < target_cpu_interface->hppi.prio) ||
- /*
- * Multiple pending ints with same priority.
- * Implementation choice which one to signal.
- * Our implementation selects the one with the lower id.
- */
- (irqPriority[int_id] ==
target_cpu_interface->hppi.prio &&
- int_id < target_cpu_interface->hppi.intid)) {
+ /*
+ * Multiple pending ints with same priority.
+ * Implementation choice which one to signal.
+ * Our implementation selects the one with the lower id.
+ */
+ (irqPriority[int_id] == target_cpu_interface->hppi.prio &&
+ int_id < target_cpu_interface->hppi.intid)) {
target_cpu_interface->hppi.intid = int_id;
target_cpu_interface->hppi.prio = irqPriority[int_id];
target_cpu_interface->hppi.group = int_group;
@@ -1026,16 +1042,15 @@
redistributor_i->getCPUInterface();
if (!new_hppi[i] && cpu_interface_i->hppi.prio != 0xff &&
- cpu_interface_i->hppi.intid >=
- (Gicv3::SGI_MAX + Gicv3::PPI_MAX) &&
- cpu_interface_i->hppi.intid < Gicv3::INTID_SECURE) {
+ cpu_interface_i->hppi.intid >= (Gicv3::SGI_MAX +
Gicv3::PPI_MAX) &&
+ cpu_interface_i->hppi.intid < Gicv3::INTID_SECURE) {
fullUpdate();
}
}
}
Gicv3::IntStatus
-Gicv3Distributor::intStatus(uint32_t int_id)
+Gicv3Distributor::intStatus(uint32_t int_id) const
{
panic_if(int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX, "Invalid SPI!");
panic_if(int_id > itLines, "Invalid SPI!");
@@ -1054,7 +1069,7 @@
}
Gicv3::GroupId
-Gicv3Distributor::getIntGroup(int int_id)
+Gicv3Distributor::getIntGroup(int int_id) const
{
panic_if(int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX, "Invalid SPI!");
panic_if(int_id > itLines, "Invalid SPI!");
diff --git a/src/dev/arm/gic_v3_distributor.hh
b/src/dev/arm/gic_v3_distributor.hh
index 334ecee..6b7b0cb 100644
--- a/src/dev/arm/gic_v3_distributor.hh
+++ b/src/dev/arm/gic_v3_distributor.hh
@@ -106,21 +106,21 @@
static const AddrRange GICD_IROUTER;
BitUnion64(IROUTER)
- Bitfield<63, 40> res0_1;
- Bitfield<39, 32> Aff3;
- Bitfield<31> IRM;
- Bitfield<30, 24> res0_2;
- Bitfield<23, 16> Aff2;
- Bitfield<15, 8> Aff1;
- Bitfield<7, 0> Aff0;
+ Bitfield<63, 40> res0_1;
+ Bitfield<39, 32> Aff3;
+ Bitfield<31> IRM;
+ Bitfield<30, 24> res0_2;
+ Bitfield<23, 16> Aff2;
+ Bitfield<15, 8> Aff1;
+ Bitfield<7, 0> Aff0;
EndBitUnion(IROUTER)
- static const uint32_t GICD_CTLR_ENABLEGRP0 = 1 << 0;
+ static const uint32_t GICD_CTLR_ENABLEGRP0 = 1 << 0;
+ static const uint32_t GICD_CTLR_ENABLEGRP1 = 1 << 0;
static const uint32_t GICD_CTLR_ENABLEGRP1NS = 1 << 1;
- static const uint32_t GICD_CTLR_ENABLEGRP1S = 1 << 2;
- static const uint32_t GICD_CTLR_ENABLEGRP1 = 1 << 0;
- static const uint32_t GICD_CTLR_ENABLEGRP1A = 1 << 1;
- static const uint32_t GICD_CTLR_DS = 1 << 6;
+ static const uint32_t GICD_CTLR_ENABLEGRP1A = 1 << 1;
+ static const uint32_t GICD_CTLR_ENABLEGRP1S = 1 << 2;
+ static const uint32_t GICD_CTLR_DS = 1 << 6;
bool ARE;
bool DS;
@@ -141,19 +141,15 @@
static const uint32_t ADDR_RANGE_SIZE = 0x10000;
- Gicv3Distributor(Gicv3 * gic, uint32_t it_lines);
- ~Gicv3Distributor();
- void init();
- void initState();
+ protected:
- uint64_t read(Addr addr, size_t size, bool is_secure_access);
- void write(Addr addr, uint64_t data, size_t size,
- bool is_secure_access);
- void serialize(CheckpointOut & cp) const override;
- void unserialize(CheckpointIn & cp) override;
+ void activateIRQ(uint32_t int_id);
+ void deactivateIRQ(uint32_t int_id);
+ void fullUpdate();
+ Gicv3::GroupId getIntGroup(int int_id) const;
- bool
- groupEnabled(Gicv3::GroupId group)
+ inline bool
+ groupEnabled(Gicv3::GroupId group) const
{
if (DS == 0) {
switch (group) {
@@ -186,16 +182,9 @@
}
}
- void sendInt(uint32_t int_id);
- void intDeasserted(uint32_t int_id);
- Gicv3::IntStatus intStatus(uint32_t int_id);
- void updateAndInformCPUInterfaces();
- void update();
- void fullUpdate();
- void activateIRQ(uint32_t int_id);
- void deactivateIRQ(uint32_t int_id);
+ Gicv3::IntStatus intStatus(uint32_t int_id) const;
- inline bool isNotSPI(uint8_t int_id)
+ inline bool isNotSPI(uint8_t int_id) const
{
if (int_id < (Gicv3::SGI_MAX + Gicv3::PPI_MAX) || int_id >=
itLines) {
return true;
@@ -204,15 +193,28 @@
}
}
- inline bool nsAccessToSecInt(uint8_t int_id, bool is_secure_access)
+ inline bool nsAccessToSecInt(uint8_t int_id, bool is_secure_access)
const
{
return !DS && !is_secure_access && getIntGroup(int_id) !=
Gicv3::G1NS;
}
- protected:
-
void reset();
- Gicv3::GroupId getIntGroup(int int_id);
+ void serialize(CheckpointOut & cp) const override;
+ void unserialize(CheckpointIn & cp) override;
+ void update();
+ void updateAndInformCPUInterfaces();
+
+ public:
+
+ Gicv3Distributor(Gicv3 * gic, uint32_t it_lines);
+
+ void deassertSPI(uint32_t int_id);
+ void init();
+ void initState();
+ uint64_t read(Addr addr, size_t size, bool is_secure_access);
+ void sendInt(uint32_t int_id);
+ void write(Addr addr, uint64_t data, size_t size,
+ bool is_secure_access);
};
#endif //__DEV_ARM_GICV3_DISTRIBUTOR_H__
diff --git a/src/dev/arm/gic_v3_redistributor.cc
b/src/dev/arm/gic_v3_redistributor.cc
index ec1e388..81d58e2 100644
--- a/src/dev/arm/gic_v3_redistributor.cc
+++ b/src/dev/arm/gic_v3_redistributor.cc
@@ -36,7 +36,7 @@
#include "dev/arm/gic_v3_distributor.hh"
const AddrRange Gicv3Redistributor::GICR_IPRIORITYR(SGI_base + 0x0400,
- SGI_base + 0x041f);
+ SGI_base + 0x041f);
Gicv3Redistributor::Gicv3Redistributor(Gicv3 * gic, uint32_t cpu_id)
: gic(gic),
@@ -54,10 +54,6 @@
{
}
-Gicv3Redistributor::~Gicv3Redistributor()
-{
-}
-
void
Gicv3Redistributor::init()
{
@@ -166,7 +162,7 @@
uint64_t affinity = getAffinity();
int last = cpuId == (gic->getSystem()->numContexts() - 1);
return (affinity << 32) | (1 << 24) | (cpuId << 8) |
- (1 << 5) | (last << 4);
+ (1 << 5) | (last << 4);
}
case GICR_WAKER: // Wake Register
@@ -182,8 +178,7 @@
}
case GICR_PIDR0: { // Peripheral ID0 Register
- uint8_t part_0 = 0x92; // Part number, bits[7:0]
- return part_0;
+ return 0x92; // Part number, bits[7:0]
}
case GICR_PIDR1: { // Peripheral ID1 Register
@@ -290,7 +285,7 @@
uint32_t first_int_id = addr == GICR_ICFGR0 ? 0 : Gicv3::SGI_MAX;
for (int i = 0, int_id = first_int_id; i < 32;
- i = i + 2, int_id++) {
+ i = i + 2, int_id++) {
if (!distributor->DS && !is_secure_access) {
// RAZ/WI for non-secure accesses for secure interrupts
if (getIntGroup(int_id) != Gicv3::G1NS) {
@@ -337,7 +332,7 @@
value = 0;
} else {
for (int i = 0, int_id = 0; i < 8 * size;
- i = i + 2, int_id++) {
+ i = i + 2, int_id++) {
value |= irqNsacr[int_id] << i;
}
}
@@ -396,11 +391,11 @@
}
if (not peInLowPowerState and
- (data & GICR_WAKER_ProcessorSleep)) {
+ (data & GICR_WAKER_ProcessorSleep)) {
DPRINTF(GIC, "Gicv3Redistributor::write(): "
"PE entering in low power state\n");
} else if (peInLowPowerState and
- not(data & GICR_WAKER_ProcessorSleep)) {
+ not(data & GICR_WAKER_ProcessorSleep)) {
DPRINTF(GIC, "Gicv3Redistributor::write(): powering up PE\n");
}
@@ -553,7 +548,7 @@
int first_intid = Gicv3::SGI_MAX;
for (int i = 0, int_id = first_intid; i < 8 * size;
- i = i + 2, int_id++) {
+ i = i + 2, int_id++) {
if (!distributor->DS && !is_secure_access) {
// RAZ/WI for non-secure accesses for secure interrupts
if (getIntGroup(int_id) != Gicv3::G1NS) {
@@ -561,9 +556,9 @@
}
}
- irqConfig[int_id] = data & (0x2 << i)
- ? Gicv3::INT_EDGE_TRIGGERED :
- Gicv3::INT_LEVEL_SENSITIVE;
+ irqConfig[int_id] = data & (0x2 << i) ?
+ Gicv3::INT_EDGE_TRIGGERED :
+ Gicv3::INT_LEVEL_SENSITIVE;
DPRINTF(GIC, "Gicv3Redistributor::write(): "
"int_id %d (PPI) config %d\n",
int_id, irqConfig[int_id]);
@@ -597,7 +592,7 @@
// RAZ/WI
} else {
for (int i = 0, int_id = 0; i < 8 * size;
- i = i + 2, int_id++) {
+ i = i + 2, int_id++) {
irqNsacr[int_id] = (data >> i) & 0x3;
}
}
@@ -644,7 +639,7 @@
int nsaccess = irqNsacr[int_id];
if ((int_group == Gicv3::G0S && nsaccess < 1) ||
- (int_group == Gicv3::G1S && nsaccess < 2)) {
+ (int_group == Gicv3::G1S && nsaccess < 2)) {
return;
}
}
@@ -656,7 +651,7 @@
}
Gicv3::IntStatus
-Gicv3Redistributor::intStatus(uint32_t int_id)
+Gicv3Redistributor::intStatus(uint32_t int_id) const
{
assert(int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX);
@@ -689,13 +684,13 @@
if (irqPending[int_id] && irqEnabled[int_id] &&
!irqActive[int_id] && group_enabled) {
if ((irqPriority[int_id] < cpuInterface->hppi.prio) ||
- /*
- * Multiple pending ints with same priority.
- * Implementation choice which one to signal.
- * Our implementation selects the one with the lower
id.
- */
- (irqPriority[int_id] == cpuInterface->hppi.prio &&
- int_id < cpuInterface->hppi.intid)) {
+ /*
+ * Multiple pending ints with same priority.
+ * Implementation choice which one to signal.
+ * Our implementation selects the one with the lower id.
+ */
+ (irqPriority[int_id] == cpuInterface->hppi.prio &&
+ int_id < cpuInterface->hppi.intid)) {
cpuInterface->hppi.intid = int_id;
cpuInterface->hppi.prio = irqPriority[int_id];
cpuInterface->hppi.group = int_group;
@@ -705,7 +700,7 @@
}
if (!new_hppi && cpuInterface->hppi.prio != 0xff &&
- cpuInterface->hppi.intid < Gicv3::SGI_MAX + Gicv3::PPI_MAX) {
+ cpuInterface->hppi.intid < Gicv3::SGI_MAX + Gicv3::PPI_MAX) {
distributor->fullUpdate();
}
}
@@ -718,7 +713,7 @@
}
Gicv3::GroupId
-Gicv3Redistributor::getIntGroup(int int_id)
+Gicv3Redistributor::getIntGroup(int int_id) const
{
assert(int_id < (Gicv3::SGI_MAX + Gicv3::PPI_MAX));
@@ -757,7 +752,7 @@
}
uint32_t
-Gicv3Redistributor::getAffinity()
+Gicv3Redistributor::getAffinity() const
{
ThreadContext * tc = gic->getSystem()->getThreadContext(cpuId);
uint64_t mpidr = getMPIDR(gic->getSystem(), tc);
@@ -774,7 +769,7 @@
}
bool
-Gicv3Redistributor::canBeSelectedFor1toNInterrupt(Gicv3::GroupId group)
+Gicv3Redistributor::canBeSelectedFor1toNInterrupt(Gicv3::GroupId group)
const
{
if (peInLowPowerState) {
return false;
diff --git a/src/dev/arm/gic_v3_redistributor.hh
b/src/dev/arm/gic_v3_redistributor.hh
index 1155397..ccafde2 100644
--- a/src/dev/arm/gic_v3_redistributor.hh
+++ b/src/dev/arm/gic_v3_redistributor.hh
@@ -35,8 +35,8 @@
#include "dev/arm/gic_v3.hh"
#include "sim/serialize.hh"
-class Gicv3Distributor;
class Gicv3CPUInterface;
+class Gicv3Distributor;
class Gicv3Redistributor : public Serializable
{
@@ -56,14 +56,14 @@
* GICv3 defines 2 contiguous 64KB frames for each redistributor.
* Order of frames must be RD_base, SGI_base.
*/
- static const uint32_t RD_base = 0x0;
+ static const uint32_t RD_base = 0x0;
static const uint32_t SGI_base = 0x10000;
enum {
// Control Register
GICR_CTLR = RD_base + 0x0000,
// Implementer Identification Register
- GICR_IIDR = RD_base + 0x0004,
+ GICR_IIDR = RD_base + 0x0004,
// Type Register
GICR_TYPER = RD_base + 0x0008,
// Wake Register
@@ -99,21 +99,21 @@
// Interrupt Clear-Enable Register 0
GICR_ICENABLER0 = SGI_base + 0x0180,
// Interrupt Set-Pending Register 0
- GICR_ISPENDR0 = SGI_base + 0x0200,
+ GICR_ISPENDR0 = SGI_base + 0x0200,
// Interrupt Clear-Pending Register 0
- GICR_ICPENDR0 = SGI_base + 0x0280,
+ GICR_ICPENDR0 = SGI_base + 0x0280,
// Interrupt Set-Active Register 0
GICR_ISACTIVER0 = SGI_base + 0x0300,
// Interrupt Clear-Active Register 0
GICR_ICACTIVER0 = SGI_base + 0x0380,
// SGI Configuration Register
- GICR_ICFGR0 = SGI_base + 0x0c00,
+ GICR_ICFGR0 = SGI_base + 0x0c00,
// PPI Configuration Register
- GICR_ICFGR1 = SGI_base + 0x0c04,
+ GICR_ICFGR1 = SGI_base + 0x0c04,
// Interrupt Group Modifier Register 0
- GICR_IGRPMODR0 = SGI_base + 0x0d00,
+ GICR_IGRPMODR0 = SGI_base + 0x0d00,
// Non-secure Access Control Register
- GICR_NSACR = SGI_base + 0x0e00,
+ GICR_NSACR = SGI_base + 0x0e00,
};
// Interrupt Priority Registers
@@ -132,9 +132,9 @@
bool DPG1NS;
bool DPG0;
- static const uint32_t GICR_CTLR_DPG0 = 1 << 24;
+ static const uint32_t GICR_CTLR_DPG0 = 1 << 24;
static const uint32_t GICR_CTLR_DPG1NS = 1 << 25;
- static const uint32_t GICR_CTLR_DPG1S = 1 << 26;
+ static const uint32_t GICR_CTLR_DPG1S = 1 << 26;
public:
@@ -147,37 +147,37 @@
*/
static const uint32_t ADDR_RANGE_SIZE = 0x40000;
- Gicv3Redistributor(Gicv3 * gic, uint32_t cpu_id);
- ~Gicv3Redistributor();
- void init();
- void initState();
+ protected:
- uint64_t read(Addr addr, size_t size, bool is_secure_access);
- void write(Addr addr, uint64_t data, size_t size,
- bool is_secure_access);
- void sendPPInt(uint32_t int_id);
- void sendSGI(uint32_t int_id, Gicv3::GroupId group, bool ns);
- void serialize(CheckpointOut & cp) const override;
- void unserialize(CheckpointIn & cp) override;
- uint32_t getAffinity();
+ void activateIRQ(uint32_t int_id);
+ bool canBeSelectedFor1toNInterrupt(Gicv3::GroupId group) const;
+ void deactivateIRQ(uint32_t int_id);
- Gicv3CPUInterface *
+ inline Gicv3CPUInterface *
getCPUInterface() const
{
return cpuInterface;
}
- bool canBeSelectedFor1toNInterrupt(Gicv3::GroupId group);
-
- protected:
-
+ Gicv3::GroupId getIntGroup(int int_id) const;
+ Gicv3::IntStatus intStatus(uint32_t int_id) const;
void reset();
+ void sendSGI(uint32_t int_id, Gicv3::GroupId group, bool ns);
+ void serialize(CheckpointOut & cp) const override;
+ void unserialize(CheckpointIn & cp) override;
void update();
void updateAndInformCPUInterface();
- Gicv3::IntStatus intStatus(uint32_t int_id);
- Gicv3::GroupId getIntGroup(int int_id);
- void activateIRQ(uint32_t int_id);
- void deactivateIRQ(uint32_t int_id);
+
+ public:
+
+ Gicv3Redistributor(Gicv3 * gic, uint32_t cpu_id);
+
+ uint32_t getAffinity() const;
+ void init();
+ void initState();
+ uint64_t read(Addr addr, size_t size, bool is_secure_access);
+ void sendPPInt(uint32_t int_id);
+ void write(Addr addr, uint64_t data, size_t size, bool
is_secure_access);
};
#endif //__DEV_ARM_GICV3_REDISTRIBUTOR_H__
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I9aba90022f6408838c4ab87c6b90bba438752e53
Gerrit-Change-Number: 16222
Gerrit-PatchSet: 1
Gerrit-Owner: Jairo Balart <[email protected]>
Gerrit-MessageType: newchange
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