Javier Bueno Hedo has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/16583
Change subject: mem-cache: Added extra information to PrefetchInfo
......................................................................
mem-cache: Added extra information to PrefetchInfo
Added additional information to the PrefetchInfo data structure
- Whether the event is triggered by a cache miss
- Whether the event is a write or a read
- Size of the data accessed
- Data accessed by the request
Change-Id: I070f3ffe837ea960a357388e7f2b8a61d7b2196c
---
M src/mem/cache/prefetch/base.cc
M src/mem/cache/prefetch/base.hh
2 files changed, 97 insertions(+), 23 deletions(-)
diff --git a/src/mem/cache/prefetch/base.cc b/src/mem/cache/prefetch/base.cc
index cd3eade..7cc2b30 100644
--- a/src/mem/cache/prefetch/base.cc
+++ b/src/mem/cache/prefetch/base.cc
@@ -56,23 +56,29 @@
#include "params/BasePrefetcher.hh"
#include "sim/system.hh"
-BasePrefetcher::PrefetchInfo::PrefetchInfo(PacketPtr pkt, Addr addr)
+BasePrefetcher::PrefetchInfo::PrefetchInfo(PacketPtr pkt, Addr addr, bool
miss)
: address(addr), pc(pkt->req->hasPC() ? pkt->req->getPC() : 0),
masterId(pkt->req->masterId()), validPC(pkt->req->hasPC()),
- secure(pkt->isSecure())
+ secure(pkt->isSecure()), size(pkt->req->getSize()),
write(pkt->isWrite()),
+ paddress(pkt->req->getPaddr()), cacheMiss(miss)
{
+ unsigned int req_size = pkt->req->getSize();
+ data = new uint8_t[req_size];
+ Addr offset = pkt->req->getPaddr() - pkt->getAddr();
+ std::memcpy(data, &(pkt->getConstPtr<uint8_t>()[offset]), req_size);
}
BasePrefetcher::PrefetchInfo::PrefetchInfo(PrefetchInfo const &pfi, Addr
addr)
: address(addr), pc(pfi.pc), masterId(pfi.masterId),
validPC(pfi.validPC),
- secure(pfi.secure)
+ secure(pfi.secure), size(pfi.size), write(pfi.write),
+ paddress(pfi.paddress), cacheMiss(pfi.cacheMiss), data(nullptr)
{
}
void
BasePrefetcher::PrefetchListener::notify(const PacketPtr &pkt)
{
- parent.probeNotify(pkt);
+ parent.probeNotify(pkt, miss);
}
BasePrefetcher::BasePrefetcher(const BasePrefetcherParams *p)
@@ -110,13 +116,11 @@
}
bool
-BasePrefetcher::observeAccess(const PacketPtr &pkt) const
+BasePrefetcher::observeAccess(const PacketPtr &pkt, bool miss) const
{
- Addr addr = pkt->getAddr();
bool fetch = pkt->req->isInstFetch();
bool read = pkt->isRead();
bool inv = pkt->isInvalidate();
- bool is_secure = pkt->isSecure();
if (pkt->req->isUncacheable()) return false;
if (fetch && !onInst) return false;
@@ -127,8 +131,7 @@
if (pkt->cmd == MemCmd::CleanEvict) return false;
if (onMiss) {
- return !inCache(addr, is_secure) &&
- !inMissQueue(addr, is_secure);
+ return miss;
}
return true;
@@ -189,25 +192,26 @@
}
void
-BasePrefetcher::probeNotify(const PacketPtr &pkt)
+BasePrefetcher::probeNotify(const PacketPtr &pkt, bool miss)
{
// Don't notify prefetcher on SWPrefetch, cache maintenance
// operations or for writes that we are coaslescing.
if (pkt->cmd.isSWPrefetch()) return;
if (pkt->req->isCacheMaintenance()) return;
if (pkt->isWrite() && cache != nullptr && cache->coalesce()) return;
+ if (!pkt->req->hasPaddr()) return;
if (hasBeenPrefetched(pkt->getAddr(), pkt->isSecure())) {
usefulPrefetches += 1;
}
// Verify this access type is observed by prefetcher
- if (observeAccess(pkt)) {
+ if (observeAccess(pkt, miss)) {
if (useVirtualAddresses && pkt->req->hasVaddr()) {
- PrefetchInfo pfi(pkt, pkt->req->getVaddr());
+ PrefetchInfo pfi(pkt, pkt->req->getVaddr(), miss);
notify(pkt, pfi);
- } else if (!useVirtualAddresses && pkt->req->hasPaddr()) {
- PrefetchInfo pfi(pkt, pkt->req->getPaddr());
+ } else if (!useVirtualAddresses) {
+ PrefetchInfo pfi(pkt, pkt->req->getPaddr(), miss);
notify(pkt, pfi);
}
}
@@ -223,9 +227,9 @@
*/
if (listeners.empty() && cache != nullptr) {
ProbeManager *pm(cache->getProbeManager());
- listeners.push_back(new PrefetchListener(*this, pm, "Miss"));
+ listeners.push_back(new PrefetchListener(*this, pm, "Miss", true));
if (prefetchOnAccess) {
- listeners.push_back(new PrefetchListener(*this, pm, "Hit"));
+ listeners.push_back(new PrefetchListener(*this, pm, "Hit",
false));
}
}
}
diff --git a/src/mem/cache/prefetch/base.hh b/src/mem/cache/prefetch/base.hh
index de275f8..3a45080 100644
--- a/src/mem/cache/prefetch/base.hh
+++ b/src/mem/cache/prefetch/base.hh
@@ -67,12 +67,13 @@
{
public:
PrefetchListener(BasePrefetcher &_parent, ProbeManager *pm,
- const std::string &name)
+ const std::string &name, bool miss = false)
: ProbeListenerArgBase(pm, name),
parent(_parent) {}
void notify(const PacketPtr &pkt) override;
protected:
BasePrefetcher &parent;
+ bool miss;
};
std::vector<PrefetchListener *> listeners;
@@ -84,7 +85,7 @@
* generate new prefetch requests.
*/
class PrefetchInfo {
- /** The address. */
+ /** The address used to train and generate prefetches */
Addr address;
/** The program counter that generated this address. */
Addr pc;
@@ -94,6 +95,16 @@
bool validPC;
/** Whether this address targets the secure memory space. */
bool secure;
+ /** Size in bytes of the request triggering this event */
+ unsigned int size;
+ /** Whether this event comes from a write request */
+ bool write;
+ /** Physical address, needed because address can be virtual */
+ Addr paddress;
+ /** Whether this event comes from a cache miss */
+ bool cacheMiss;
+ /** Pointer to the associated request data */
+ uint8_t *data;
public:
/**
@@ -143,6 +154,53 @@
}
/**
+ * Gets the size of the request triggering this event
+ * @return the size in bytes of the request triggering this event
+ */
+ unsigned int getSize() const
+ {
+ return size;
+ }
+
+ /**
+ * Checks if the request that caused this prefetch event was a
write
+ * request
+ * @return true if the request causing this event is a write
request
+ */
+ bool isWrite() const
+ {
+ return write;
+ }
+
+ /**
+ * Gets the physical address of the request
+ * @return physical address of the request
+ */
+ Addr getPaddr() const
+ {
+ return paddress;
+ }
+
+ /**
+ * Check if this event comes from a cache miss
+ * @result true if this event comes from a cache miss
+ */
+ bool isCacheMiss() const
+ {
+ return cacheMiss;
+ }
+
+ /**
+ * Copies the associated data of the request triggering the event
to
+ * the provided memory location.
+ * @return pointer to copy the data
+ */
+ void getData(uint8_t *ptr) const
+ {
+ std::memcpy(ptr, data, size);
+ }
+
+ /**
* Check for equality
* @param pfi PrefetchInfo to compare against
* @return True if this object and the provided one are equal
@@ -156,9 +214,11 @@
/**
* Constructs a PrefetchInfo using a PacketPtr.
* @param pkt PacketPtr used to generate the PrefetchInfo
- * @param addr the address value of the new object
+ * @param addr the address value of the new object, this address is
+ * used to train the prefetcher
+ * @param miss whether this event comes from a cache miss
*/
- PrefetchInfo(PacketPtr pkt, Addr addr);
+ PrefetchInfo(PacketPtr pkt, Addr addr, bool miss);
/**
* Constructs a PrefetchInfo using a new address value and
@@ -167,6 +227,11 @@
* @param addr the address value of the new object
*/
PrefetchInfo(PrefetchInfo const &pfi, Addr addr);
+
+ ~PrefetchInfo()
+ {
+ delete data;
+ }
};
protected:
@@ -208,8 +273,12 @@
/** Use Virtual Addresses for prefetching */
const bool useVirtualAddresses;
- /** Determine if this access should be observed */
- bool observeAccess(const PacketPtr &pkt) const;
+ /**
+ * Determine if this access should be observed
+ * @param pkt The memory request causing the event
+ * @param miss whether this event comes from a cache miss
+ */
+ bool observeAccess(const PacketPtr &pkt, bool miss) const;
/** Determine if address is in cache */
bool inCache(Addr addr, bool is_secure) const;
@@ -270,8 +339,9 @@
/**
* Process a notification event from the ProbeListener.
* @param pkt The memory request causing the event
+ * @param miss whether this event comes from a cache miss
*/
- void probeNotify(const PacketPtr &pkt);
+ void probeNotify(const PacketPtr &pkt, bool miss);
/**
* Add a SimObject and a probe name to listen events from
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16583
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I070f3ffe837ea960a357388e7f2b8a61d7b2196c
Gerrit-Change-Number: 16583
Gerrit-PatchSet: 1
Gerrit-Owner: Javier Bueno Hedo <[email protected]>
Gerrit-MessageType: newchange
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
