Sandipan Das has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/16616

Change subject: arch-power: Add fixed-point word arithmetic modulo instructions
......................................................................

arch-power: Add fixed-point word arithmetic modulo instructions

This adds the following arithmetic instructions:
  * Modulo Signed Word (modsw)
  * Modulo Unsigned Word (moduw)

Change-Id: I5590e569afb71dd429c473bd18c65457e2c49286
Signed-off-by: Sandipan Das <[email protected]>
---
M src/arch/power/isa/decoder.isa
M src/arch/power/isa/formats/integer.isa
2 files changed, 33 insertions(+), 0 deletions(-)



diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index 8c46ac2..7241130 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -380,6 +380,28 @@
             181: stdux({{ Mem = Rs; }});
         }

+        format IntArithOp {
+            779: modsw({{
+                int64_t src1 = Ra_sw;
+                int64_t src2 = Rb_sw;
+                if ((src1 != INT32_MIN || src2 != -1) && src2 != 0) {
+                    Rt = src1 % src2;
+                } else {
+                    Rt = 0;
+                }
+            }});
+
+            267: moduw({{
+                uint64_t src1 = Ra_uw;
+                uint64_t src2 = Rb_uw;
+                if (src2 != 0) {
+                    Rt = src1 % src2;
+                } else {
+                    Rt = 0;
+                }
+            }});
+        }
+
         format IntOp {
             0: cmp({{
                 Xer xer = XER;
diff --git a/src/arch/power/isa/formats/integer.isa b/src/arch/power/isa/formats/integer.isa
index b4ec74f..9bbd65e 100644
--- a/src/arch/power/isa/formats/integer.isa
+++ b/src/arch/power/isa/formats/integer.isa
@@ -325,6 +325,17 @@


 // Instructions that use source registers Ra and Rb, with the result
+// placed into Rt but do not check for carry, overflow or the Rc bit.
+def format IntArithOp(code, inst_flags = []) {{
+
+    # Generate the class
+    (header_output, decoder_output, decode_block, exec_output) = \
+        GenAluOp(name, Name, 'IntArithOp', code, inst_flags, BasicDecode,
+                 BasicConstructor)
+}};
+
+
+// Instructions that use source registers Ra and Rb, with the result
 // placed into Rt. Basically multiply and divide instructions. The
 // carry bit is never set, but overflow can be calculated. In certain
 // situations, the overflow bits have to be set and this is dealt with

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I5590e569afb71dd429c473bd18c65457e2c49286
Gerrit-Change-Number: 16616
Gerrit-PatchSet: 1
Gerrit-Owner: Sandipan Das <[email protected]>
Gerrit-MessageType: newchange
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