Sandipan Das has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/16629
Change subject: arch-power: Add fixed-point logical count zeros instructions
......................................................................
arch-power: Add fixed-point logical count zeros instructions
This adds the following logical instructions:
* Count Trailing Zeros Word (cnttzw[.])
* Count Leading Zeros Doubleword (cntlzd[.])
* Count Trailing Zeros Doubleword (cnttzd[.])
Change-Id: I4bcf090178d9241f230509ba55e8e58f5e7794ac
Signed-off-by: Sandipan Das <[email protected]>
---
M src/arch/power/insts/integer.cc
M src/arch/power/insts/integer.hh
M src/arch/power/isa/decoder.isa
3 files changed, 60 insertions(+), 1 deletion(-)
diff --git a/src/arch/power/insts/integer.cc
b/src/arch/power/insts/integer.cc
index f87afa2..6f190d3 100644
--- a/src/arch/power/insts/integer.cc
+++ b/src/arch/power/insts/integer.cc
@@ -293,7 +293,10 @@
} else if (!myMnemonic.compare("extsb") ||
!myMnemonic.compare("extsh") ||
!myMnemonic.compare("extsw") ||
- !myMnemonic.compare("cntlzw")) {
+ !myMnemonic.compare("cntlzw") ||
+ !myMnemonic.compare("cntlzd") ||
+ !myMnemonic.compare("cnttzw") ||
+ !myMnemonic.compare("cnttzd")) {
printSecondSrc = false;
}
diff --git a/src/arch/power/insts/integer.hh
b/src/arch/power/insts/integer.hh
index 7db9165..d8c7507 100644
--- a/src/arch/power/insts/integer.hh
+++ b/src/arch/power/insts/integer.hh
@@ -506,6 +506,8 @@
{
}
+ /* Compute the number of consecutive zero bits starting from the
+ leftmost bit and moving right in a 32-bit integer */
inline int
findLeadingZeros(uint32_t rs) const
{
@@ -521,6 +523,57 @@
}
}
+ /* Compute the number of consecutive zero bits starting from the
+ leftmost bit and moving right in a 64-bit integer */
+ inline int
+ findLeadingZeros(uint64_t rs) const
+ {
+ if (rs) {
+ #if defined(__GNUC__) || (defined(__clang__) && \
+ __has_builtin(__builtin_clzll))
+ return __builtin_clzll(rs);
+ #else
+ return 63 - findMsbSet(rs);
+ #endif
+ } else {
+ return 64;
+ }
+ }
+
+ /* Compute the number of consecutive zero bits starting from the
+ rightmost bit and moving left in a 32-bit integer */
+ inline int
+ findTrailingZeros(uint32_t rs) const
+ {
+ if (rs) {
+ #if defined(__GNUC__) || (defined(__clang__) && \
+ __has_builtin(__builtin_ctz))
+ return __builtin_ctz(rs);
+ #else
+ return findLsbSet(rs);
+ #endif
+ } else {
+ return 32;
+ }
+ }
+
+ /* Compute the number of consecutive zero bits starting from the
+ rightmost bit and moving left in a 64-bit integer */
+ inline int
+ findTrailingZeros(uint64_t rs) const
+ {
+ if (rs) {
+ #if defined(__GNUC__) || (defined(__clang__) && \
+ __has_builtin(__builtin_ctzll))
+ return __builtin_ctzll(rs);
+ #else
+ return findLsbSet(rs);
+ #endif
+ } else {
+ return 64;
+ }
+ }
+
std::string generateDisassembly(
Addr pc, const SymbolTable *symtab) const override;
};
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index e1221bb..71aa52c 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -517,6 +517,9 @@
922: extsh({{ Ra = Rs_sh; }}, true);
986: extsw({{ Ra = Rs_sw; }}, true);
26: cntlzw({{ Ra = findLeadingZeros(Rs_uw); }}, true);
+ 58: cntlzd({{ Ra = findLeadingZeros(Rs); }}, true);
+ 538: cnttzw({{ Ra = findTrailingZeros(Rs_uw); }}, true);
+ 570: cnttzd({{ Ra = findTrailingZeros(Rs); }}, true);
508: cmpb({{
uint64_t mask = 0xff;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I4bcf090178d9241f230509ba55e8e58f5e7794ac
Gerrit-Change-Number: 16629
Gerrit-PatchSet: 1
Gerrit-Owner: Sandipan Das <[email protected]>
Gerrit-MessageType: newchange
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