Sandipan Das has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/16643
Change subject: arch-power: Fix special-purpose register definitions
......................................................................
arch-power: Fix special-purpose register definitions
This converts the definitions of all the currently defined
Special Purpose Registers (SPRs) to miscellaneous registers
which allows us to print the corresponding SPR name in the
debug logs rather than an ambiguous register number making
things much easier to correlate.
This also fixes disassembly generation for the move to and
from instructions corresponding to some of the SPRs.
Change-Id: I4c477e886adac5761cd9e9228bcdebd958ee22eb
Signed-off-by: Sandipan Das <[email protected]>
---
M src/arch/power/insts/integer.cc
M src/arch/power/isa.hh
M src/arch/power/isa/operands.isa
M src/arch/power/miscregs.hh
M src/arch/power/process.cc
M src/arch/power/registers.hh
M src/arch/power/remote_gdb.cc
7 files changed, 87 insertions(+), 40 deletions(-)
diff --git a/src/arch/power/insts/integer.cc
b/src/arch/power/insts/integer.cc
index 1a74b80..1c85a41 100644
--- a/src/arch/power/insts/integer.cc
+++ b/src/arch/power/insts/integer.cc
@@ -48,9 +48,17 @@
if (!myMnemonic.compare("or") && _srcRegIdx[0] == _srcRegIdx[1]) {
myMnemonic = "mr";
printSecondSrc = false;
- } else if (!myMnemonic.compare("mtlr")) {
+ } else if (!myMnemonic.compare("mtcrf") ||
+ !myMnemonic.compare("mtxer") ||
+ !myMnemonic.compare("mtlr") ||
+ !myMnemonic.compare("mtctr") ||
+ !myMnemonic.compare("mttar")) {
printDest = false;
- } else if (!myMnemonic.compare("mflr")) {
+ } else if (!myMnemonic.compare("mfcr") ||
+ !myMnemonic.compare("mfxer") ||
+ !myMnemonic.compare("mflr") ||
+ !myMnemonic.compare("mfctr") ||
+ !myMnemonic.compare("mftar")) {
printSrcs = false;
}
diff --git a/src/arch/power/isa.hh b/src/arch/power/isa.hh
index 16850d1..bb3e6f8 100644
--- a/src/arch/power/isa.hh
+++ b/src/arch/power/isa.hh
@@ -37,6 +37,7 @@
#include "arch/power/types.hh"
#include "base/logging.hh"
#include "cpu/reg_class.hh"
+#include "debug/MiscRegs.hh"
#include "sim/sim_object.hh"
struct PowerISAParams;
@@ -62,32 +63,64 @@
}
RegVal
- readMiscRegNoEffect(int misc_reg) const
+ readMiscRegNoEffect(int miscReg) const
{
- fatal("Power does not currently have any misc regs defined\n");
- return dummy;
+ assert(miscReg < NumMiscRegs);
+ int flatIndex = flattenMiscIndex(miscReg);
+ auto regVal = miscRegs[flatIndex];
+ auto regName = miscRegName[flatIndex];
+ DPRINTF(MiscRegs, "Reading misc reg %d (%s) as %#x.\n", miscReg,
+ regName, regVal);
+ return regVal;
}
RegVal
- readMiscReg(int misc_reg, ThreadContext *tc)
+ readMiscReg(int miscReg, ThreadContext *tc)
{
- fatal("Power does not currently have any misc regs defined\n");
- return dummy;
+ return readMiscRegNoEffect(miscReg);
}
void
- setMiscRegNoEffect(int misc_reg, RegVal val)
+ setMiscRegNoEffect(int miscReg, RegVal regVal)
{
- fatal("Power does not currently have any misc regs defined\n");
+ assert(miscReg < NumMiscRegs);
+ int flatIndex = flattenMiscIndex(miscReg);
+ auto regName = miscRegName[flatIndex];
+ DPRINTF(MiscRegs, "Setting misc reg %d (%s) to %#x.\n", miscReg,
+ regName, regVal);
+ miscRegs[flatIndex] = regVal;
}
void
- setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
+ setMiscReg(int miscReg, RegVal regVal, ThreadContext *tc)
{
- fatal("Power does not currently have any misc regs defined\n");
+ return setMiscRegNoEffect(miscReg, regVal);
}
- RegId flattenRegId(const RegId& regId) const { return regId; }
+ RegId
+ flattenRegId(const RegId& regId) const
+ {
+ switch (regId.classValue()) {
+ case IntRegClass:
+ return RegId(IntRegClass, flattenIntIndex(regId.index()));
+ case FloatRegClass:
+ return RegId(FloatRegClass,
flattenFloatIndex(regId.index()));
+ case VecRegClass:
+ return RegId(VecRegClass, flattenVecIndex(regId.index()));
+ case VecElemClass:
+ return RegId(VecElemClass,
flattenVecElemIndex(regId.index()),
+ regId.elemIndex());
+ case VecPredRegClass:
+ return RegId(VecPredRegClass,
+ flattenVecPredIndex(regId.index()));
+ case CCRegClass:
+ return RegId(CCRegClass, flattenCCIndex(regId.index()));
+ case MiscRegClass:
+ return RegId(MiscRegClass,
flattenMiscIndex(regId.index()));
+ }
+
+ return RegId();
+ }
int
flattenIntIndex(int reg) const
diff --git a/src/arch/power/isa/operands.isa
b/src/arch/power/isa/operands.isa
index d45cc11..4219668 100644
--- a/src/arch/power/isa/operands.isa
+++ b/src/arch/power/isa/operands.isa
@@ -64,14 +64,14 @@
'NIA': ('PCState', 'ud', 'npc', (None, None, 'IsControl'), 9),
# Control registers
- 'CR': ('IntReg', 'uw', 'INTREG_CR', 'IsInteger', 9),
- 'XER': ('IntReg', 'uw', 'INTREG_XER', 'IsInteger', 9),
- 'LR': ('IntReg', 'ud', 'INTREG_LR', 'IsInteger', 9),
- 'CTR': ('IntReg', 'ud', 'INTREG_CTR', 'IsInteger', 9),
- 'TAR': ('IntReg', 'ud', 'INTREG_TAR', 'IsInteger', 9),
+ 'CR': ('ControlReg', 'uw', 'MISCREG_CR', 'IsInteger', 9),
+ 'XER': ('ControlReg', 'uw', 'MISCREG_XER', 'IsInteger', 9),
+ 'LR': ('ControlReg', 'ud', 'MISCREG_LR', 'IsInteger', 9),
+ 'CTR': ('ControlReg', 'ud', 'MISCREG_CTR', 'IsInteger', 9),
+ 'TAR': ('ControlReg', 'ud', 'MISCREG_TAR', 'IsInteger', 9),
- # Setting as IntReg so things are stored as an integer, not double
- 'FPSCR': ('IntReg', 'uw', 'INTREG_FPSCR', 'IsFloating', 9),
+ # Setting as ControlReg so things are stored as an integer, not double
+ 'FPSCR': ('ControlReg', 'uw', 'MISCREG_FPSCR', 'IsFloating', 9),
# Registers for linked loads and stores
'Rsv': ('IntReg', 'uw', 'INTREG_RSV', 'IsInteger', 9),
diff --git a/src/arch/power/miscregs.hh b/src/arch/power/miscregs.hh
index 444f88e..56f3848 100644
--- a/src/arch/power/miscregs.hh
+++ b/src/arch/power/miscregs.hh
@@ -37,10 +37,22 @@
{
enum MiscRegIndex {
- NUM_MISCREGS = 0
+ MISCREG_CR,
+ MISCREG_FPSCR,
+ MISCREG_XER,
+ MISCREG_LR,
+ MISCREG_CTR,
+ MISCREG_TAR,
+ NUM_MISCREGS
};
const char * const miscRegName[NUM_MISCREGS] = {
+ "CR",
+ "FPSCR",
+ "XER",
+ "LR",
+ "CTR",
+ "TAR"
};
BitUnion32(Cr)
diff --git a/src/arch/power/process.cc b/src/arch/power/process.cc
index 5301846..ce59891 100644
--- a/src/arch/power/process.cc
+++ b/src/arch/power/process.cc
@@ -323,12 +323,12 @@
void
PowerProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret)
{
- Cr cr = tc->readIntReg(INTREG_CR);
+ Cr cr = tc->readMiscReg(MISCREG_CR);
if (sysret.successful()) {
cr.cr0.so = 0;
} else {
cr.cr0.so = 1;
}
- tc->setIntReg(INTREG_CR, cr);
+ tc->setMiscReg(MISCREG_CR, cr);
tc->setIntReg(ReturnValueReg, sysret.encodedValue());
}
diff --git a/src/arch/power/registers.hh b/src/arch/power/registers.hh
index a7702ee..5c8f027 100644
--- a/src/arch/power/registers.hh
+++ b/src/arch/power/registers.hh
@@ -64,9 +64,9 @@
// Constants Related to the number of registers
const int NumIntArchRegs = 32;
-// CR, XER, LR, CTR, TAR, FPSCR, RSV, RSV-LEN, RSV-ADDR
+// RSV, RSV-LEN, RSV-ADDR
// and zero register, which doesn't actually exist but needs a number
-const int NumIntSpecialRegs = 10;
+const int NumIntSpecialRegs = 4;
const int NumFloatArchRegs = 32;
const int NumFloatSpecialRegs = 0;
const int NumInternalProcRegs = 0;
@@ -98,13 +98,7 @@
const int SyscallSuccessReg = 3;
enum MiscIntRegNums {
- INTREG_CR = NumIntArchRegs,
- INTREG_XER,
- INTREG_LR,
- INTREG_CTR,
- INTREG_TAR,
- INTREG_FPSCR,
- INTREG_RSV,
+ INTREG_RSV = NumIntArchRegs,
INTREG_RSV_LEN,
INTREG_RSV_ADDR
};
diff --git a/src/arch/power/remote_gdb.cc b/src/arch/power/remote_gdb.cc
index d4824c6..f87fcaf 100644
--- a/src/arch/power/remote_gdb.cc
+++ b/src/arch/power/remote_gdb.cc
@@ -189,10 +189,10 @@
r.pc = htog(context->pcState().pc());
r.msr = 0; // Is MSR modeled?
- r.cr = htog((uint32_t)context->readIntReg(INTREG_CR));
- r.lr = htog(context->readIntReg(INTREG_LR));
- r.ctr = htog(context->readIntReg(INTREG_CTR));
- r.xer = htog((uint32_t)context->readIntReg(INTREG_XER));
+ r.cr = htog((uint32_t)context->readIntReg(MISCREG_CR));
+ r.lr = htog(context->readIntReg(MISCREG_LR));
+ r.ctr = htog(context->readIntReg(MISCREG_CTR));
+ r.xer = htog((uint32_t)context->readIntReg(MISCREG_XER));
}
void
@@ -208,10 +208,10 @@
context->pcState(gtoh(r.pc));
// Is MSR modeled?
- context->setIntReg(INTREG_CR, gtoh(r.cr));
- context->setIntReg(INTREG_LR, gtoh(r.lr));
- context->setIntReg(INTREG_CTR, gtoh(r.ctr));
- context->setIntReg(INTREG_XER, gtoh(r.xer));
+ context->setIntReg(MISCREG_CR, gtoh(r.cr));
+ context->setIntReg(MISCREG_LR, gtoh(r.lr));
+ context->setIntReg(MISCREG_CTR, gtoh(r.ctr));
+ context->setIntReg(MISCREG_XER, gtoh(r.xer));
}
BaseGdbRegCache*
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I4c477e886adac5761cd9e9228bcdebd958ee22eb
Gerrit-Change-Number: 16643
Gerrit-PatchSet: 1
Gerrit-Owner: Sandipan Das <[email protected]>
Gerrit-MessageType: newchange
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