Sandipan Das has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/16644
Change subject: arch-power: Remove redundant zero register updates
......................................................................
arch-power: Remove redundant zero register updates
This removes redundant updates of the zero register for the
Power architecture. This architecture does not define a zero
register even though the simulator mandates having one. So,
there is no point in setting it to zero everytime during the
pre-execute stage.
Change-Id: I359100dd2a02976e42d783b8bf0c0aff5d2597e9
Signed-off-by: Sandipan Das <[email protected]>
---
M src/cpu/simple/base.cc
1 file changed, 3 insertions(+), 0 deletions(-)
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 422c732..beb2c3d 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -490,8 +490,11 @@
SimpleExecContext &t_info = *threadInfo[curThread];
SimpleThread* thread = t_info.thread;
+#if THE_ISA != POWER_ISA
// maintain $r0 semantics
thread->setIntReg(ZeroReg, 0);
+#endif // POWER_ISA
+
#if THE_ISA == ALPHA_ISA
thread->setFloatReg(ZeroReg, 0);
#endif // ALPHA_ISA
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I359100dd2a02976e42d783b8bf0c0aff5d2597e9
Gerrit-Change-Number: 16644
Gerrit-PatchSet: 1
Gerrit-Owner: Sandipan Das <[email protected]>
Gerrit-MessageType: newchange
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