Hello Andreas Sandberg,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/16749
to review the following change.
Change subject: dev: StreamID generation in DMA device
......................................................................
dev: StreamID generation in DMA device
This patch is adding a StreamID tag to any DMA Packet. StreamIDs are
tags which are used by IOMMUs to distinguish between different
devices/functions.
For PCI devices for example, the RID (Pci Bus number, Pci Device
number, Pci Function number) could be stored in the Packet streamID
field.
For the MemObject base class, a simple pair of (Sub)StreamIDs has been
provided. This is basically attaching a fixed (decided at python config
time) streamID per device. If a derived device wants to implement a
more elaborate packet tagger (for example if it wants to have more than
one streamID), it needs to pass a different StreamID and SubstreamID to
the DmaPort interface (like dmaAction).
Change-Id: Ia17cf00437f7d3eb79211c1374134b174f90de59
Signed-off-by: Giacomo Travaglini <[email protected]>
Reviewed-by: Andreas Sandberg <[email protected]>
---
M src/dev/dma_device.cc
M src/dev/dma_device.hh
M src/mem/MemObject.py
3 files changed, 67 insertions(+), 10 deletions(-)
diff --git a/src/dev/dma_device.cc b/src/dev/dma_device.cc
index c445fbc..7fb7462 100644
--- a/src/dev/dma_device.cc
+++ b/src/dev/dma_device.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012, 2015, 2017 ARM Limited
+ * Copyright (c) 2012, 2015, 2017, 2019 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -57,7 +57,9 @@
: MasterPort(dev->name() + ".dma", dev),
device(dev), sys(s), masterId(s->getMasterId(dev)),
sendEvent([this]{ sendDma(); }, dev->name()),
- pendingCount(0), inRetry(false)
+ pendingCount(0), inRetry(false),
+ defaultSid(dev->params()->sid),
+ defaultSSid(dev->params()->ssid)
{ }
void
@@ -147,7 +149,8 @@
RequestPtr
DmaPort::dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
- uint8_t *data, Tick delay, Request::Flags flag)
+ uint8_t *data, uint32_t sid, uint32_t ssid, Tick delay,
+ Request::Flags flag)
{
// one DMA request sender state for every action, that is then
// split into many requests and packets based on the block size,
@@ -168,6 +171,9 @@
req = std::make_shared<Request>(
gen.addr(), gen.size(), flag, masterId);
+ req->setStreamId(sid);
+ req->setSubStreamId(ssid);
+
req->taskId(ContextSwitchTaskId::DMA);
PacketPtr pkt = new Packet(req, cmd);
@@ -190,6 +196,14 @@
return req;
}
+RequestPtr
+DmaPort::dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
+ uint8_t *data, Tick delay, Request::Flags flag)
+{
+ return dmaAction(cmd, addr, size, event, data,
+ defaultSid, defaultSSid, delay, flag);
+}
+
void
DmaPort::queueDma(PacketPtr pkt)
{
@@ -271,10 +285,6 @@
return PioDevice::getMasterPort(if_name, idx);
}
-
-
-
-
DmaReadFifo::DmaReadFifo(DmaPort &_port, size_t size,
unsigned max_req_size,
unsigned max_pending,
diff --git a/src/dev/dma_device.hh b/src/dev/dma_device.hh
index 0dc79df..6683433 100644
--- a/src/dev/dma_device.hh
+++ b/src/dev/dma_device.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012-2013, 2015, 2017 ARM Limited
+ * Copyright (c) 2012-2013, 2015, 2017, 2019 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -132,6 +132,12 @@
* send whatever it is that it's sending. */
bool inRetry;
+ /** Default streamId */
+ uint32_t defaultSid;
+
+ /** Default substreamId */
+ uint32_t defaultSSid;
+
protected:
bool recvTimingResp(PacketPtr pkt) override;
@@ -143,8 +149,14 @@
DmaPort(MemObject *dev, System *s);
- RequestPtr dmaAction(Packet::Command cmd, Addr addr, int size, Event
*event,
- uint8_t *data, Tick delay, Request::Flags flag =
0);
+ RequestPtr
+ dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
+ uint8_t *data, Tick delay, Request::Flags flag = 0);
+
+ RequestPtr
+ dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
+ uint8_t *data, uint32_t sid, uint32_t ssid, Tick delay,
+ Request::Flags flag = 0);
bool dmaPending() const { return pendingCount > 0; }
@@ -162,12 +174,26 @@
virtual ~DmaDevice() { }
void dmaWrite(Addr addr, int size, Event *event, uint8_t *data,
+ uint32_t sid, uint32_t ssid, Tick delay = 0)
+ {
+ dmaPort.dmaAction(MemCmd::WriteReq, addr, size, event, data,
+ sid, ssid, delay);
+ }
+
+ void dmaWrite(Addr addr, int size, Event *event, uint8_t *data,
Tick delay = 0)
{
dmaPort.dmaAction(MemCmd::WriteReq, addr, size, event, data,
delay);
}
void dmaRead(Addr addr, int size, Event *event, uint8_t *data,
+ uint32_t sid, uint32_t ssid, Tick delay = 0)
+ {
+ dmaPort.dmaAction(MemCmd::ReadReq, addr, size, event, data,
+ sid, ssid, delay);
+ }
+
+ void dmaRead(Addr addr, int size, Event *event, uint8_t *data,
Tick delay = 0)
{
dmaPort.dmaAction(MemCmd::ReadReq, addr, size, event, data, delay);
diff --git a/src/mem/MemObject.py b/src/mem/MemObject.py
index 42d561d..fd10ab9 100644
--- a/src/mem/MemObject.py
+++ b/src/mem/MemObject.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2019 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
@@ -25,10 +37,19 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Ron Dreslinski
+# Giacomo Travaglini
from m5.objects.ClockedObject import ClockedObject
+from m5.params import *
class MemObject(ClockedObject):
type = 'MemObject'
abstract = True
cxx_header = "mem/mem_object.hh"
+
+ sid = Param.Unsigned(0,
+ "Stream identifier used by an IOMMU to distinguish amongst "
+ "several devices attached to it")
+ ssid = Param.Unsigned(0,
+ "Substream identifier used by an IOMMU to distinguish amongst "
+ "several devices attached to it")
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16749
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ia17cf00437f7d3eb79211c1374134b174f90de59
Gerrit-Change-Number: 16749
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-MessageType: newchange
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