Giacomo Travaglini has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/16545 )
Change subject: dev-arm: Set ICV_PMR_EL1-ICH_VMCR_EL2 mapping on reads
......................................................................
dev-arm: Set ICV_PMR_EL1-ICH_VMCR_EL2 mapping on reads
Reading ICV_PMR_EL1 should return the value the VMCR_EL2.VPMR bits
which are aliased to the register.
Change-Id: Id3e6dfb196f3726edaa3eddb244765598ed62334
Signed-off-by: Giacomo Travaglini <[email protected]>
Reviewed-by: Jan-Peter Larsson <[email protected]>
Reviewed-by: Andreas Sandberg <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/c/16545
Maintainer: Andreas Sandberg <[email protected]>
---
M src/dev/arm/gic_v3_cpu_interface.cc
1 file changed, 23 insertions(+), 2 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
diff --git a/src/dev/arm/gic_v3_cpu_interface.cc
b/src/dev/arm/gic_v3_cpu_interface.cc
index f00a86a..3f6c23f 100644
--- a/src/dev/arm/gic_v3_cpu_interface.cc
+++ b/src/dev/arm/gic_v3_cpu_interface.cc
@@ -388,7 +388,7 @@
case MISCREG_ICC_PMR_EL1: // Priority Mask Register
if ((currEL() == EL1) && !inSecureState() &&
(hcr_imo || hcr_fmo)) {
- return isa->readMiscRegNoEffect(MISCREG_ICV_PMR_EL1);
+ return readMiscReg(MISCREG_ICV_PMR_EL1);
}
if (haveEL(EL3) && !inSecureState() &&
@@ -406,6 +406,14 @@
break;
+ case MISCREG_ICV_PMR_EL1: { // Priority Mask Register
+ RegVal ich_vmcr_el2 =
+ isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
+
+ value = ich_vmcr_el2 >> ICH_VMCR_EL2_VPMR_SHIFT;
+ break;
+ }
+
case MISCREG_ICC_IAR0:
case MISCREG_ICC_IAR0_EL1: { // Interrupt Acknowledge Register 0
if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
@@ -1268,7 +1276,7 @@
case MISCREG_ICC_PMR_EL1: { // Priority Mask Register
if ((currEL() == EL1) && !inSecureState() &&
(hcr_imo || hcr_fmo)) {
- return isa->setMiscRegNoEffect(MISCREG_ICV_PMR_EL1, val);
+ return setMiscReg(MISCREG_ICV_PMR_EL1, val);
}
val &= 0xff;
@@ -1295,6 +1303,19 @@
break;
}
+ case MISCREG_ICV_PMR_EL1: { // Priority Mask Register
+ RegVal ich_vmcr_el2 =
+ isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
+ ich_vmcr_el2 = insertBits(
+ ich_vmcr_el2,
+ ICH_VMCR_EL2_VPMR_SHIFT + ICH_VMCR_EL2_VPMR_LENGTH - 1,
+ ICH_VMCR_EL2_VPMR_SHIFT, val);
+
+ isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
+ virtualUpdate();
+ return;
+ }
+
case MISCREG_ICC_IGRPEN0:
case MISCREG_ICC_IGRPEN0_EL1: { // Interrupt Group 0 Enable Register
if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Id3e6dfb196f3726edaa3eddb244765598ed62334
Gerrit-Change-Number: 16545
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-MessageType: merged
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