Giacomo Gabrielli has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/13515 )
Change subject: arch-arm,cpu: Add initial support for Arm SVE
......................................................................
arch-arm,cpu: Add initial support for Arm SVE
This changeset adds initial support for the Arm Scalable Vector Extension
(SVE) by implementing:
- support for most data-processing instructions (no loads/stores yet);
- basic system-level support.
Additional authors:
- Javier Setoain <[email protected]>
- Gabor Dozsa <[email protected]>
- Giacomo Travaglini <[email protected]>
Thanks to Pau Cabre for his contribution of bugfixes.
Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709
Signed-off-by: Giacomo Gabrielli <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13515
Reviewed-by: Andreas Sandberg <[email protected]>
Maintainer: Andreas Sandberg <[email protected]>
---
M src/arch/arm/ArmISA.py
M src/arch/arm/ArmSystem.py
M src/arch/arm/SConscript
M src/arch/arm/decoder.cc
M src/arch/arm/decoder.hh
M src/arch/arm/insts/static_inst.cc
M src/arch/arm/insts/static_inst.hh
A src/arch/arm/insts/sve.cc
A src/arch/arm/insts/sve.hh
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/isa/formats/formats.isa
A src/arch/arm/isa/formats/sve_2nd_level.isa
A src/arch/arm/isa/formats/sve_top_level.isa
M src/arch/arm/isa/includes.isa
M src/arch/arm/isa/insts/fp64.isa
M src/arch/arm/isa/insts/insts.isa
M src/arch/arm/isa/insts/ldr64.isa
M src/arch/arm/isa/insts/mem.isa
M src/arch/arm/isa/insts/neon64.isa
M src/arch/arm/isa/insts/neon64_mem.isa
A src/arch/arm/isa/insts/sve.isa
M src/arch/arm/isa/operands.isa
A src/arch/arm/isa/templates/sve.isa
M src/arch/arm/isa/templates/templates.isa
M src/arch/arm/miscregs.cc
M src/arch/arm/miscregs.hh
M src/arch/arm/miscregs_types.hh
M src/arch/arm/nativetrace.cc
M src/arch/arm/process.cc
M src/arch/arm/registers.hh
M src/arch/arm/system.cc
M src/arch/arm/system.hh
M src/arch/arm/types.hh
M src/arch/arm/utility.cc
M src/arch/arm/utility.hh
M src/arch/generic/vec_reg.hh
M src/cpu/FuncUnit.py
M src/cpu/exetrace.cc
M src/cpu/minor/MinorCPU.py
M src/cpu/o3/FUPool.py
M src/cpu/o3/FuncUnitConfig.py
M src/cpu/op_class.hh
M src/cpu/simple_thread.cc
A util/cpt_upgraders/arm-sve.py
46 files changed, 11,605 insertions(+), 61 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709
Gerrit-Change-Number: 13515
Gerrit-PatchSet: 18
Gerrit-Owner: Giacomo Gabrielli <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Anthony Gutierrez <[email protected]>
Gerrit-Reviewer: Giacomo Gabrielli <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-CC: Daniel Carvalho <[email protected]>
Gerrit-MessageType: merged
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