Andrea Mondelli has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/17248
Change subject: misc: Removed inconsistency in BPRED* debug msgs
......................................................................
misc: Removed inconsistency in BPRED* debug msgs
- Added consistency in the DEBUG message form, to allow a better parsing
- Added SN number information to some DEBUG msg for tracing purpose
Change-Id: I4761c49fc12b874a7d8b46779475b606865cad4b
---
M src/arch/mips/isa.cc
M src/cpu/o3/commit_impl.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/decode_impl.hh
M src/cpu/o3/fetch_impl.hh
M src/cpu/o3/iew_impl.hh
M src/cpu/o3/inst_queue_impl.hh
M src/cpu/o3/rename_impl.hh
M src/cpu/o3/rob_impl.hh
M src/cpu/pred/bpred_unit.cc
M src/cpu/pred/indirect.cc
M src/cpu/pred/indirect.hh
12 files changed, 211 insertions(+), 175 deletions(-)
diff --git a/src/arch/mips/isa.cc b/src/arch/mips/isa.cc
index 2711712..eaee294 100644
--- a/src/arch/mips/isa.cc
+++ b/src/arch/mips/isa.cc
@@ -450,7 +450,7 @@
unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
? tid : getVPENum(tid);
DPRINTF(MipsPRA,
- "[tid:%i]: Setting (direct set) CP0 Register:%u "
+ "[tid:%i] Setting (direct set) CP0 Register:%u "
"Select:%u (%s) to %#x.\n",
tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
@@ -463,7 +463,7 @@
unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
? tid : getVPENum(tid);
DPRINTF(MipsPRA,
- "[tid:%i]: Setting CP0 Register: %u Select: %u (%s) to %#x\n",
+ "[tid:%i] Setting CP0 Register: %u Select: %u (%s) to %#x\n",
tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
miscRegFile_WriteMask[misc_reg][reg_sel] = val;
}
@@ -479,7 +479,7 @@
? tid : getVPENum(tid);
DPRINTF(MipsPRA,
- "[tid:%i]: Setting CP0 Register:%u "
+ "[tid:%i] Setting CP0 Register:%u "
"Select:%u (%s) to %#x, with effect.\n",
tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index ec3d610..434f148 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -704,7 +704,7 @@
const DynInstPtr &inst M5_VAR_USED = rob->readHeadInst(tid);
- DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head
of"
+ DPRINTF(Commit,"[tid:%i] Instruction [sn:%lli] PC %s is head
of"
" ROB and ready to commit\n",
tid, inst->seqNum, inst->pcState());
@@ -713,12 +713,12 @@
ppCommitStall->notify(inst);
- DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli]
PC "
+ DPRINTF(Commit,"[tid:%i] Can't commit, Instruction [sn:%lli]
PC "
"%s is head of ROB and not ready\n",
tid, inst->seqNum, inst->pcState());
}
- DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
+ DPRINTF(Commit, "[tid:%i] ROB has %d insts & %d free entries.\n",
tid, rob->countInsts(tid), rob->numFreeEntries(tid));
}
@@ -862,17 +862,18 @@
if (fromIEW->mispredictInst[tid]) {
DPRINTF(Commit,
- "[tid:%i]: Squashing due to branch mispred PC:%#x
[sn:%i]\n",
+ "[tid:%i] Squashing due to branch mispred "
+ "PC:%#x [sn:%i]\n",
tid,
fromIEW->mispredictInst[tid]->instAddr(),
fromIEW->squashedSeqNum[tid]);
} else {
DPRINTF(Commit,
- "[tid:%i]: Squashing due to order violation [sn:%i]\n",
+ "[tid:%i] Squashing due to order violation [sn:%i]\n",
tid, fromIEW->squashedSeqNum[tid]);
}
- DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
+ DPRINTF(Commit, "[tid:%i] Redirecting to PC %#x\n",
tid,
fromIEW->pc[tid].nextInstAddr());
@@ -1364,7 +1365,7 @@
for (int inst_num = 0; inst_num < fromIEW->size; ++inst_num) {
assert(fromIEW->insts[inst_num]);
if (!fromIEW->insts[inst_num]->isSquashed()) {
- DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready "
+ DPRINTF(Commit, "[tid:%i] Marking PC %s, [sn:%lli] ready "
"within ROB.\n",
fromIEW->insts[inst_num]->threadNumber,
fromIEW->insts[inst_num]->pcState(),
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 965ab04..5c88c50 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -689,11 +689,11 @@
list<ThreadID>::iterator isActive =
std::find(activeThreads.begin(), activeThreads.end(), tid);
- DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid);
+ DPRINTF(O3CPU, "[tid:%i] Calling activate thread.\n", tid);
assert(!switchedOut());
if (isActive == activeThreads.end()) {
- DPRINTF(O3CPU, "[tid:%i]: Adding to active threads list\n",
+ DPRINTF(O3CPU, "[tid:%i] Adding to active threads list\n",
tid);
activeThreads.push_back(tid);
@@ -708,11 +708,11 @@
list<ThreadID>::iterator thread_it =
std::find(activeThreads.begin(), activeThreads.end(), tid);
- DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid);
+ DPRINTF(O3CPU, "[tid:%i] Calling deactivate thread.\n", tid);
assert(!switchedOut());
if (thread_it != activeThreads.end()) {
- DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n",
+ DPRINTF(O3CPU,"[tid:%i] Removing from active threads list\n",
tid);
activeThreads.erase(thread_it);
}
@@ -790,7 +790,7 @@
void
FullO3CPU<Impl>::suspendContext(ThreadID tid)
{
- DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
+ DPRINTF(O3CPU,"[tid:%i] Suspending Thread Context.\n", tid);
assert(!switchedOut());
deactivateThread(tid);
@@ -812,7 +812,7 @@
FullO3CPU<Impl>::haltContext(ThreadID tid)
{
//For now, this is the same as deallocate
- DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating\n", tid);
+ DPRINTF(O3CPU,"[tid:%i] Halt Context called. Deallocating\n", tid);
assert(!switchedOut());
deactivateThread(tid);
diff --git a/src/cpu/o3/decode_impl.hh b/src/cpu/o3/decode_impl.hh
index 27b3c30..050b9db 100644
--- a/src/cpu/o3/decode_impl.hh
+++ b/src/cpu/o3/decode_impl.hh
@@ -238,7 +238,7 @@
bool ret_val = false;
if (stalls[tid].rename) {
- DPRINTF(Decode,"[tid:%i]: Stall fom Rename stage detected.\n",
tid);
+ DPRINTF(Decode,"[tid:%i] Stall fom Rename stage detected.\n", tid);
ret_val = true;
}
@@ -305,7 +305,7 @@
void
DefaultDecode<Impl>::squash(const DynInstPtr &inst, ThreadID tid)
{
- DPRINTF(Decode, "[tid:%i]: [sn:%i] Squashing due to incorrect branch "
+ DPRINTF(Decode, "[tid:%i] [sn:%i] Squashing due to incorrect branch "
"prediction detected at decode.\n", tid, inst->seqNum);
// Send back mispredict information.
@@ -357,7 +357,7 @@
unsigned
DefaultDecode<Impl>::squash(ThreadID tid)
{
- DPRINTF(Decode, "[tid:%i]: Squashing.\n",tid);
+ DPRINTF(Decode, "[tid:%i] Squashing.\n",tid);
if (decodeStatus[tid] == Blocked ||
decodeStatus[tid] == Unblocking) {
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 8afe623..6b1a62e 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -572,15 +572,18 @@
nextPC, tid);
if (predict_taken) {
- DPRINTF(Fetch, "[tid:%i]: [sn:%i]: Branch predicted to be taken
to %s.\n",
- tid, inst->seqNum, nextPC);
+ DPRINTF(Fetch, "[tid:%i] [sn:%i] Branch at PC %#x "
+ "predicted to be taken to %s\n",
+ tid, inst->seqNum, inst->pcState().instAddr(), nextPC);
} else {
- DPRINTF(Fetch, "[tid:%i]: [sn:%i]:Branch predicted to be not
taken.\n",
- tid, inst->seqNum);
+ DPRINTF(Fetch, "[tid:%i] [sn:%i] Branch at PC %#x "
+ "predicted to be not taken\n",
+ tid, inst->seqNum, inst->pcState().instAddr());
}
- DPRINTF(Fetch, "[tid:%i]: [sn:%i] Branch predicted to go to %s.\n",
- tid, inst->seqNum, nextPC);
+ DPRINTF(Fetch, "[tid:%i] [sn:%i] Branch at PC %#x "
+ "predicted to go to %s\n",
+ tid, inst->seqNum, inst->pcState().instAddr(), nextPC);
inst->setPredTarg(nextPC);
inst->setPredTaken(predict_taken);
@@ -699,8 +702,8 @@
retryTid = tid;
cacheBlocked = true;
} else {
- DPRINTF(Fetch, "[tid:%i]: Doing Icache access.\n", tid);
- DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache "
+ DPRINTF(Fetch, "[tid:%i] Doing Icache access.\n", tid);
+ DPRINTF(Activity, "[tid:%i] Activity: Waiting on I-cache "
"response.\n", tid);
lastIcacheStall[tid] = curTick();
fetchStatus[tid] = IcacheWaitResponse;
@@ -728,7 +731,7 @@
// wake up is if a squash comes along and changes the PC.
TheISA::PCState fetchPC = pc[tid];
- DPRINTF(Fetch, "[tid:%i]: Translation faulted, building noop.\n",
tid);
+ DPRINTF(Fetch, "[tid:%i] Translation faulted, building noop.\n",
tid);
// We will use a nop in ordier to carry the fault.
DynInstPtr instruction = buildInst(tid,
StaticInst::nopStaticInstPtr,
NULL, fetchPC, fetchPC, false);
@@ -743,8 +746,8 @@
fetchStatus[tid] = TrapPending;
- DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",
tid);
- DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %s.\n",
+ DPRINTF(Fetch, "[tid:%i] Blocked, need to handle the trap.\n",
tid);
+ DPRINTF(Fetch, "[tid:%i] fault (%s) detected @ PC %s.\n",
tid, fault->name(), pc[tid]);
}
_status = updateFetchStatus();
@@ -755,7 +758,7 @@
DefaultFetch<Impl>::doSquash(const TheISA::PCState &newPC,
const DynInstPtr squashInst, ThreadID tid)
{
- DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %s.\n",
+ DPRINTF(Fetch, "[tid:%i] Squashing, setting PC to: %s.\n",
tid, newPC);
pc[tid] = newPC;
@@ -768,11 +771,11 @@
// Clear the icache miss if it's outstanding.
if (fetchStatus[tid] == IcacheWaitResponse) {
- DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
+ DPRINTF(Fetch, "[tid:%i] Squashing outstanding Icache miss.\n",
tid);
memReq[tid] = NULL;
} else if (fetchStatus[tid] == ItlbWait) {
- DPRINTF(Fetch, "[tid:%i]: Squashing outstanding ITLB miss.\n",
+ DPRINTF(Fetch, "[tid:%i] Squashing outstanding ITLB miss.\n",
tid);
memReq[tid] = NULL;
}
@@ -808,7 +811,7 @@
const DynInstPtr squashInst,
const InstSeqNum seq_num, ThreadID
tid)
{
- DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n", tid);
+ DPRINTF(Fetch, "[tid:%i] Squashing from decode.\n", tid);
doSquash(newPC, squashInst, tid);
@@ -825,7 +828,7 @@
if (stalls[tid].drain) {
assert(cpu->isDraining());
- DPRINTF(Fetch,"[tid:%i]: Drain stall detected.\n",tid);
+ DPRINTF(Fetch,"[tid:%i] Drain stall detected.\n",tid);
ret_val = true;
}
@@ -848,10 +851,10 @@
fetchStatus[tid] == IcacheAccessComplete) {
if (_status == Inactive) {
- DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid);
+ DPRINTF(Activity, "[tid:%i] Activating stage.\n",tid);
if (fetchStatus[tid] == IcacheAccessComplete) {
- DPRINTF(Activity, "[tid:%i]: Activating fetch due to
cache"
+ DPRINTF(Activity, "[tid:%i] Activating fetch due to
cache"
"completion\n",tid);
}
@@ -962,8 +965,8 @@
if (!stalls[tid].decode && !fetchQueue[tid].empty()) {
const auto& inst = fetchQueue[tid].front();
toDecode->insts[toDecode->size++] = inst;
- DPRINTF(Fetch, "[tid:%i][sn:%i]: Sending instruction to decode
from "
- "fetch queue. Fetch queue size: %i.\n",
+ DPRINTF(Fetch, "[tid:%i] [sn:%i] Sending instruction to
decode "
+ "from fetch queue. Fetch queue size: %i.\n",
tid, inst->seqNum, fetchQueue[tid].size());
wroteToTimeBuffer = true;
@@ -1069,7 +1072,7 @@
fetchStatus[tid] != IcacheWaitRetry &&
fetchStatus[tid] != ItlbWait &&
fetchStatus[tid] != QuiescePending) {
- DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid);
+ DPRINTF(Fetch, "[tid:%i] Setting to blocked\n",tid);
fetchStatus[tid] = Blocked;
@@ -1080,7 +1083,7 @@
fetchStatus[tid] == Squashing) {
// Switch status to running if fetch isn't being told to block or
// squash this cycle.
- DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n",
+ DPRINTF(Fetch, "[tid:%i] Done squashing, switching to running.\n",
tid);
fetchStatus[tid] = Running;
@@ -1111,11 +1114,11 @@
instruction->setThreadState(cpu->thread[tid]);
- DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x (%d) created "
+ DPRINTF(Fetch, "[tid:%i] Instruction PC %#x (%d) created "
"[sn:%lli].\n", tid, thisPC.instAddr(),
thisPC.microPC(), seq);
- DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n", tid,
+ DPRINTF(Fetch, "[tid:%i] Instruction is: %s\n", tid,
instruction->staticInst->
disassemble(thisPC.instAddr()));
@@ -1137,7 +1140,7 @@
assert(numInst < fetchWidth);
fetchQueue[tid].push_back(instruction);
assert(fetchQueue[tid].size() <= fetchQueueSize);
- DPRINTF(Fetch, "[tid:%i]: Fetch queue entry created (%i/%i).\n",
+ DPRINTF(Fetch, "[tid:%i] Fetch queue entry created (%i/%i).\n",
tid, fetchQueue[tid].size(), fetchQueueSize);
//toDecode->insts[toDecode->size++] = instruction;
@@ -1183,7 +1186,7 @@
// to running, otherwise do the cache access. Possibly move this up
// to tick() function.
if (fetchStatus[tid] == IcacheAccessComplete) {
- DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n", tid);
+ DPRINTF(Fetch, "[tid:%i] Icache miss is complete.\n", tid);
fetchStatus[tid] = Running;
status_change = true;
@@ -1196,7 +1199,7 @@
// from a macro-op, then start fetch from icache.
if (!(fetchBufferValid[tid] && fetchBufferBlockPC ==
fetchBufferPC[tid])
&& !inRom && !macroop[tid]) {
- DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read "
+ DPRINTF(Fetch, "[tid:%i] Attempting to translate and read "
"instruction, starting at PC %s.\n", tid, thisPC);
fetchCacheLine(fetchAddr, tid, thisPC.instAddr());
@@ -1213,13 +1216,13 @@
// an delayed commit micro-op currently (delayed commit
instructions
// are not interruptable by interrupts, only faults)
++fetchMiscStallCycles;
- DPRINTF(Fetch, "[tid:%i]: Fetch is stalled!\n", tid);
+ DPRINTF(Fetch, "[tid:%i] Fetch is stalled!\n", tid);
return;
}
} else {
if (fetchStatus[tid] == Idle) {
++fetchIdleCycles;
- DPRINTF(Fetch, "[tid:%i]: Fetch is idle!\n", tid);
+ DPRINTF(Fetch, "[tid:%i] Fetch is idle!\n", tid);
}
// Status is Idle, so fetch should do nothing.
@@ -1237,7 +1240,7 @@
// instructions from the rest of the cache line and put them into the
// queue heading to decode.
- DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to "
+ DPRINTF(Fetch, "[tid:%i] Adding instructions to queue to "
"decode.\n", tid);
// Need to keep track of whether or not a predicted branch
@@ -1379,13 +1382,13 @@
}
if (predictedBranch) {
- DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch "
+ DPRINTF(Fetch, "[tid:%i] Done fetching, predicted branch "
"instruction encountered.\n", tid);
} else if (numInst >= fetchWidth) {
- DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth "
+ DPRINTF(Fetch, "[tid:%i] Done fetching, reached fetch bandwidth "
"for this cycle.\n", tid);
} else if (blkOffset >= fetchBufferSize) {
- DPRINTF(Fetch, "[tid:%i]: Done fetching, reached the end of the"
+ DPRINTF(Fetch, "[tid:%i] Done fetching, reached the end of the"
"fetch buffer.\n", tid);
}
@@ -1617,7 +1620,7 @@
// Unless buffer already got the block, fetch it from icache.
if (!(fetchBufferValid[tid] && fetchBufferBlockPC ==
fetchBufferPC[tid])) {
- DPRINTF(Fetch, "[tid:%i]: Issuing a pipelined I-cache access, "
+ DPRINTF(Fetch, "[tid:%i] Issuing a pipelined I-cache access, "
"starting at PC %s.\n", tid, thisPC);
fetchCacheLine(fetchAddr, tid, thisPC.instAddr());
@@ -1639,36 +1642,37 @@
DPRINTF(Fetch, "Fetch has no active thread!\n");
} else if (fetchStatus[tid] == Blocked) {
++fetchBlockedCycles;
- DPRINTF(Fetch, "[tid:%i]: Fetch is blocked!\n", tid);
+ DPRINTF(Fetch, "[tid:%i] Fetch is blocked!\n", tid);
} else if (fetchStatus[tid] == Squashing) {
++fetchSquashCycles;
- DPRINTF(Fetch, "[tid:%i]: Fetch is squashing!\n", tid);
+ DPRINTF(Fetch, "[tid:%i] Fetch is squashing!\n", tid);
} else if (fetchStatus[tid] == IcacheWaitResponse) {
++icacheStallCycles;
- DPRINTF(Fetch, "[tid:%i]: Fetch is waiting cache response!\n",
+ DPRINTF(Fetch, "[tid:%i] Fetch is waiting cache response!\n",
tid);
} else if (fetchStatus[tid] == ItlbWait) {
++fetchTlbCycles;
- DPRINTF(Fetch, "[tid:%i]: Fetch is waiting ITLB walk to "
+ DPRINTF(Fetch, "[tid:%i] Fetch is waiting ITLB walk to "
"finish!\n", tid);
} else if (fetchStatus[tid] == TrapPending) {
++fetchPendingTrapStallCycles;
- DPRINTF(Fetch, "[tid:%i]: Fetch is waiting for a pending trap!\n",
+ DPRINTF(Fetch, "[tid:%i] Fetch is waiting for a pending trap!\n",
tid);
} else if (fetchStatus[tid] == QuiescePending) {
++fetchPendingQuiesceStallCycles;
- DPRINTF(Fetch, "[tid:%i]: Fetch is waiting for a pending quiesce "
+ DPRINTF(Fetch, "[tid:%i] Fetch is waiting for a pending quiesce "
"instruction!\n", tid);
} else if (fetchStatus[tid] == IcacheWaitRetry) {
++fetchIcacheWaitRetryStallCycles;
- DPRINTF(Fetch, "[tid:%i]: Fetch is waiting for an I-cache
retry!\n",
+ DPRINTF(Fetch, "[tid:%i] Fetch is waiting for an I-cache retry!\n",
tid);
} else if (fetchStatus[tid] == NoGoodAddr) {
- DPRINTF(Fetch, "[tid:%i]: Fetch predicted non-executable
address\n",
+ DPRINTF(Fetch, "[tid:%i] Fetch predicted non-executable
address\n",
tid);
} else {
- DPRINTF(Fetch, "[tid:%i]: Unexpected fetch stall reason
(Status: %i).\n",
- tid, fetchStatus[tid]);
+ DPRINTF(Fetch, "[tid:%i] Unexpected fetch stall reason "
+ "(Status: %i)\n",
+ tid, fetchStatus[tid]);
}
}
diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh
index 6434ec8..29a69a0 100644
--- a/src/cpu/o3/iew_impl.hh
+++ b/src/cpu/o3/iew_impl.hh
@@ -462,7 +462,7 @@
void
DefaultIEW<Impl>::squash(ThreadID tid)
{
- DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid);
+ DPRINTF(IEW, "[tid:%i] Squashing all instructions.\n", tid);
// Tell the IQ to start squashing.
instQueue.squash(tid);
@@ -472,7 +472,7 @@
updatedQueues = true;
// Clear the skid buffer in case it has any data in it.
- DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until
[sn:%i].\n",
+ DPRINTF(IEW, "[tid:%i] Removing skidbuffer instructions until
[sn:%i].\n",
tid, fromCommit->commitInfo[tid].doneSeqNum);
while (!skidBuffer[tid].empty()) {
@@ -496,8 +496,9 @@
void
DefaultIEW<Impl>::squashDueToBranch(const DynInstPtr& inst, ThreadID tid)
{
- DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s "
- "[sn:%i].\n", tid, inst->pcState(), inst->seqNum);
+ DPRINTF(IEW, "[tid:%i] [sn:%i] Squashing from a specific instruction,"
+ " PC: %s "
+ "\n", tid, inst->seqNum, inst->pcState() );
if (!toCommit->squash[tid] ||
inst->seqNum < toCommit->squashedSeqNum[tid]) {
@@ -521,7 +522,7 @@
void
DefaultIEW<Impl>::squashDueToMemOrder(const DynInstPtr& inst, ThreadID tid)
{
- DPRINTF(IEW, "[tid:%i]: Memory violation, squashing violator and
younger "
+ DPRINTF(IEW, "[tid:%i] Memory violation, squashing violator and
younger "
"insts, PC: %s [sn:%i].\n", tid, inst->pcState(),
inst->seqNum);
// Need to include inst->seqNum in the following comparison to cover
the
// corner case when a branch misprediction and a memory violation for
the
@@ -567,7 +568,7 @@
void
DefaultIEW<Impl>::unblock(ThreadID tid)
{
- DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid "
+ DPRINTF(IEW, "[tid:%i] Reading instructions out of the skid "
"buffer %u.\n",tid, tid);
// If the skid bufffer is empty, signal back to previous stages to
unblock.
@@ -575,7 +576,7 @@
if (skidBuffer[tid].empty()) {
toRename->iewUnblock[tid] = true;
wroteToTimeBuffer = true;
- DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid);
+ DPRINTF(IEW, "[tid:%i] Done unblocking.\n",tid);
dispatchStatus[tid] = Running;
}
}
@@ -669,7 +670,7 @@
insts[tid].pop();
- DPRINTF(IEW,"[tid:%i]: Inserting [sn:%lli] PC:%s into "
+ DPRINTF(IEW,"[tid:%i] Inserting [sn:%lli] PC:%s into "
"dispatch skidBuffer %i\n",tid, inst->seqNum,
inst->pcState(),tid);
@@ -764,10 +765,10 @@
bool ret_val(false);
if (fromCommit->commitInfo[tid].robSquashing) {
- DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid);
+ DPRINTF(IEW,"[tid:%i] Stall from Commit stage detected.\n",tid);
ret_val = true;
} else if (instQueue.isFull(tid)) {
- DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid);
+ DPRINTF(IEW,"[tid:%i] Stall: IQ is full.\n",tid);
ret_val = true;
}
@@ -800,7 +801,7 @@
}
if (fromCommit->commitInfo[tid].robSquashing) {
- DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid);
+ DPRINTF(IEW, "[tid:%i] ROB is still squashing.\n", tid);
dispatchStatus[tid] = Squashing;
emptyRenameInsts(tid);
@@ -816,7 +817,7 @@
if (dispatchStatus[tid] == Blocked) {
// Status from previous cycle was blocked, but there are no more
stall
// conditions. Switch over to unblocking.
- DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n",
+ DPRINTF(IEW, "[tid:%i] Done blocking, switching to unblocking.\n",
tid);
dispatchStatus[tid] = Unblocking;
@@ -829,7 +830,7 @@
if (dispatchStatus[tid] == Squashing) {
// Switch status to running if rename isn't being told to block or
// squash this cycle.
- DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n",
+ DPRINTF(IEW, "[tid:%i] Done squashing, switching to running.\n",
tid);
dispatchStatus[tid] = Running;
@@ -856,7 +857,7 @@
void
DefaultIEW<Impl>::emptyRenameInsts(ThreadID tid)
{
- DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid);
+ DPRINTF(IEW, "[tid:%i] Removing incoming rename instructions\n", tid);
while (!insts[tid].empty()) {
@@ -978,14 +979,14 @@
inst = insts_to_dispatch.front();
if (dispatchStatus[tid] == Unblocking) {
- DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from
skid "
+ DPRINTF(IEW, "[tid:%i] Issue: Examining instruction from skid "
"buffer\n", tid);
}
// Make sure there's a valid instruction there.
assert(inst);
- DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %s [sn:%lli] [tid:%i] to "
+ DPRINTF(IEW, "[tid:%i] Issue: Adding PC %s [sn:%lli] [tid:%i] to "
"IQ.\n",
tid, inst->pcState(), inst->seqNum, inst->threadNumber);
@@ -995,7 +996,7 @@
// Check for squashed instructions.
if (inst->isSquashed()) {
- DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction
encountered, "
+ DPRINTF(IEW, "[tid:%i] Issue: Squashed instruction
encountered, "
"not adding to IQ.\n", tid);
++iewDispSquashedInsts;
@@ -1017,7 +1018,7 @@
// Check for full conditions.
if (instQueue.isFull(tid)) {
- DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid);
+ DPRINTF(IEW, "[tid:%i] Issue: IQ has become full.\n", tid);
// Call function to start blocking.
block(tid);
@@ -1035,7 +1036,7 @@
if ((inst->isAtomic() && ldstQueue.sqFull(tid)) ||
(inst->isLoad() && ldstQueue.lqFull(tid)) ||
(inst->isStore() && ldstQueue.sqFull(tid))) {
- DPRINTF(IEW, "[tid:%i]: Issue: %s has become full.\n",tid,
+ DPRINTF(IEW, "[tid:%i] Issue: %s has become full.\n",tid,
inst->isLoad() ? "LQ" : "SQ");
// Call function to start blocking.
@@ -1052,7 +1053,7 @@
// Otherwise issue the instruction just fine.
if (inst->isAtomic()) {
- DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
+ DPRINTF(IEW, "[tid:%i] Issue: Memory instruction "
"encountered, adding to LSQ.\n", tid);
ldstQueue.insertStore(inst);
@@ -1070,7 +1071,7 @@
toRename->iewInfo[tid].dispatchedToSQ++;
} else if (inst->isLoad()) {
- DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
+ DPRINTF(IEW, "[tid:%i] Issue: Memory instruction "
"encountered, adding to LSQ.\n", tid);
// Reserve a spot in the load store queue for this
@@ -1083,7 +1084,7 @@
toRename->iewInfo[tid].dispatchedToLQ++;
} else if (inst->isStore()) {
- DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
+ DPRINTF(IEW, "[tid:%i] Issue: Memory instruction "
"encountered, adding to LSQ.\n", tid);
ldstQueue.insertStore(inst);
@@ -1111,7 +1112,7 @@
instQueue.insertBarrier(inst);
add_to_iq = false;
} else if (inst->isNop()) {
- DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, "
+ DPRINTF(IEW, "[tid:%i] Issue: Nop instruction encountered, "
"skipping.\n", tid);
inst->setIssued();
@@ -1129,7 +1130,7 @@
}
if (add_to_iq && inst->isNonSpeculative()) {
- DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
+ DPRINTF(IEW, "[tid:%i] Issue: Nonspeculative instruction "
"encountered, skipping.\n", tid);
// Same as non-speculative stores.
@@ -1162,7 +1163,7 @@
}
if (!insts_to_dispatch.empty()) {
- DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid);
+ DPRINTF(IEW,"[tid:%i] Issue: Bandwidth Full. Blocking.\n", tid);
block(tid);
toRename->iewUnblock[tid] = false;
}
@@ -1366,11 +1367,14 @@
if (inst->mispredicted() && !loadNotExecuted) {
fetchRedirect[tid] = true;
- DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
- DPRINTF(IEW, "Predicted target was PC: %s.\n",
- inst->readPredTarg());
- DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n",
- inst->pcState());
+ DPRINTF(IEW, "[tid:%i] [sn:%i] Execute: "
+ "Branch mispredict detected.\n",
+ tid,inst->seqNum);
+ DPRINTF(IEW, "[tid:%i] [sn:%i] Predicted target was
PC: %s\n",
+ tid,inst->seqNum,inst->readPredTarg());
+ DPRINTF(IEW, "[tid:%i] [sn:%i] Execute: "
+ "Redirecting fetch to PC: %s\n",
+ tid,inst->seqNum,inst->pcState());
// If incorrect, then signal the ROB that it must be
squashed.
squashDueToBranch(inst, tid);
@@ -1664,11 +1668,18 @@
if (inst->mispredicted()) {
fetchRedirect[tid] = true;
- DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
- DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n",
+ DPRINTF(IEW, "[tid:%i] [sn:%i] Execute: "
+ "Branch mispredict detected.\n",
+ tid,inst->seqNum);
+ DPRINTF(IEW, "[tid:%i] [sn:%i] Predicted target "
+ "was PC:%#x, NPC:%#x\n",
+ tid,inst->seqNum,
inst->predInstAddr(), inst->predNextInstAddr());
- DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x,"
- " NPC: %#x.\n", inst->nextInstAddr(),
+ DPRINTF(IEW, "[tid:%i] [sn:%i] Execute: "
+ "Redirecting fetch to PC: %#x, "
+ "NPC: %#x.\n",
+ tid,inst->seqNum,
+ inst->nextInstAddr(),
inst->nextInstAddr());
// If incorrect, then signal the ROB that it must be squashed.
squashDueToBranch(inst, tid);
diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh
index aa12297..f36ae5d 100644
--- a/src/cpu/o3/inst_queue_impl.hh
+++ b/src/cpu/o3/inst_queue_impl.hh
@@ -971,7 +971,7 @@
void
InstructionQueue<Impl>::commit(const InstSeqNum &inst, ThreadID tid)
{
- DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n",
+ DPRINTF(IQ, "[tid:%i] Committing instructions older than [sn:%i]\n",
tid,inst);
ListIt iq_it = instList[tid].begin();
@@ -1196,7 +1196,7 @@
void
InstructionQueue<Impl>::squash(ThreadID tid)
{
- DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in "
+ DPRINTF(IQ, "[tid:%i] Starting to squash instructions in "
"the IQ.\n", tid);
// Read instruction sequence number of last instruction out of the
@@ -1217,7 +1217,7 @@
ListIt squash_it = instList[tid].end();
--squash_it;
- DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n",
+ DPRINTF(IQ, "[tid:%i] Squashing until sequence number %i!\n",
tid, squashedSeqNum[tid]);
// Squash any instructions younger than the squashed sequence number
@@ -1246,7 +1246,7 @@
(squashed_inst->isMemRef() &&
!squashed_inst->memOpDone())) {
- DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %s
squashed.\n",
+ DPRINTF(IQ, "[tid:%i] Instruction [sn:%lli] PC %s squashed.\n",
tid, squashed_inst->seqNum, squashed_inst->pcState());
bool is_acq_rel = squashed_inst->isMemBarrier() &&
diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh
index c24a097..662b5d1 100644
--- a/src/cpu/o3/rename_impl.hh
+++ b/src/cpu/o3/rename_impl.hh
@@ -374,7 +374,8 @@
void
DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid)
{
- DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid);
+ DPRINTF(Rename, "[tid:%u] [squash sn:%i] Squashing instructions.\n",
+ tid,squash_seq_num);
// Clear the stall signal if rename was blocked or unblocking before.
// If it still needs to block, the blocking should happen the next
@@ -387,7 +388,9 @@
serializeInst[tid] = NULL;
} else if (renameStatus[tid] == SerializeStall) {
if (serializeInst[tid]->seqNum <= squash_seq_num) {
- DPRINTF(Rename, "Rename will resume serializing after
squash\n");
+ DPRINTF(Rename, "[tid:%u] [squash sn:%i] "
+ "Rename will resume serializing after squash\n",
+ tid,squash_seq_num);
resumeSerialize = true;
assert(serializeInst[tid]);
} else {
@@ -1010,8 +1013,10 @@
DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid);
return;
} else if (hb_it->instSeqNum > inst_seq_num) {
- DPRINTF(Rename, "[tid:%u]: Old sequence number encountered.
Ensure "
- "that a syscall happened recently.\n", tid);
+ DPRINTF(Rename, "[tid:%u] [sn:%lli] "
+ "Old sequence number encountered. "
+ "Ensure that a syscall happened recently.\n",
+ tid,inst_seq_num);
return;
}
@@ -1166,7 +1171,7 @@
int num_free = freeEntries[tid].robEntries -
(instsInProgress[tid] -
fromIEW->iewInfo[tid].dispatched);
- //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free);
+ //DPRINTF(Rename,"[tid:%i] %i rob free\n",tid,num_free);
return num_free;
}
@@ -1178,7 +1183,7 @@
int num_free = freeEntries[tid].iqEntries -
(instsInProgress[tid] -
fromIEW->iewInfo[tid].dispatched);
- //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free);
+ //DPRINTF(Rename,"[tid:%i] %i iq free\n",tid,num_free);
return num_free;
}
@@ -1242,23 +1247,23 @@
bool ret_val = false;
if (stalls[tid].iew) {
- DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid);
+ DPRINTF(Rename,"[tid:%i] Stall from IEW stage detected.\n", tid);
ret_val = true;
} else if (calcFreeROBEntries(tid) <= 0) {
- DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid);
+ DPRINTF(Rename,"[tid:%i] Stall: ROB has 0 free entries.\n", tid);
ret_val = true;
} else if (calcFreeIQEntries(tid) <= 0) {
- DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid);
+ DPRINTF(Rename,"[tid:%i] Stall: IQ has 0 free entries.\n", tid);
ret_val = true;
} else if (calcFreeLQEntries(tid) <= 0 && calcFreeSQEntries(tid) <= 0)
{
- DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid);
+ DPRINTF(Rename,"[tid:%i] Stall: LSQ has 0 free entries.\n", tid);
ret_val = true;
} else if (renameMap[tid]->numFreeEntries() <= 0) {
- DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n",
tid);
+ DPRINTF(Rename,"[tid:%i] Stall: RenameMap has 0 free entries.\n",
tid);
ret_val = true;
} else if (renameStatus[tid] == SerializeStall &&
(!emptyROB[tid] || instsInProgress[tid])) {
- DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not "
+ DPRINTF(Rename,"[tid:%i] Stall: Serialize stall and ROB is not "
"empty.\n",
tid);
ret_val = true;
@@ -1285,7 +1290,7 @@
emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB;
}
- DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, "
+ DPRINTF(Rename, "[tid:%i] Free IQ: %i, Free ROB: %i, "
"Free LQ: %i, Free SQ: %i,
FreeRM %i(%i %i %i %i %i)\n",
tid,
freeEntries[tid].iqEntries,
@@ -1299,7 +1304,7 @@
renameMap[tid]->numFreePredEntries(),
renameMap[tid]->numFreeCCEntries());
- DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n",
+ DPRINTF(Rename, "[tid:%i] %i instructions not yet in ROB\n",
tid, instsInProgress[tid]);
}
diff --git a/src/cpu/o3/rob_impl.hh b/src/cpu/o3/rob_impl.hh
index 2942c7a..1ad33fa 100644
--- a/src/cpu/o3/rob_impl.hh
+++ b/src/cpu/o3/rob_impl.hh
@@ -254,7 +254,7 @@
assert(head_inst->readyToCommit());
- DPRINTF(ROB, "[tid:%u]: Retiring head instruction, "
+ DPRINTF(ROB, "[tid:%u] Retiring head instruction, "
"instruction PC %s, [sn:%lli]\n", tid, head_inst->pcState(),
head_inst->seqNum);
@@ -323,13 +323,13 @@
ROB<Impl>::doSquash(ThreadID tid)
{
robWrites++;
- DPRINTF(ROB, "[tid:%u]: Squashing instructions until [sn:%i].\n",
+ DPRINTF(ROB, "[tid:%u] Squashing instructions until [sn:%i].\n",
tid, squashedSeqNum[tid]);
assert(squashIt[tid] != instList[tid].end());
if ((*squashIt[tid])->seqNum < squashedSeqNum[tid]) {
- DPRINTF(ROB, "[tid:%u]: Done squashing instructions.\n",
+ DPRINTF(ROB, "[tid:%u] Done squashing instructions.\n",
tid);
squashIt[tid] = instList[tid].end();
@@ -346,7 +346,7 @@
(*squashIt[tid])->seqNum > squashedSeqNum[tid];
++numSquashed)
{
- DPRINTF(ROB, "[tid:%u]: Squashing instruction PC %s, seq
num %i.\n",
+ DPRINTF(ROB, "[tid:%u] Squashing instruction PC %s, seq num %i.\n",
(*squashIt[tid])->threadNumber,
(*squashIt[tid])->pcState(),
(*squashIt[tid])->seqNum);
@@ -381,7 +381,7 @@
// Check if ROB is done squashing.
if ((*squashIt[tid])->seqNum <= squashedSeqNum[tid]) {
- DPRINTF(ROB, "[tid:%u]: Done squashing instructions.\n",
+ DPRINTF(ROB, "[tid:%u] Done squashing instructions.\n",
tid);
squashIt[tid] = instList[tid].end();
diff --git a/src/cpu/pred/bpred_unit.cc b/src/cpu/pred/bpred_unit.cc
index 2bfd901..fa2acdb 100644
--- a/src/cpu/pred/bpred_unit.cc
+++ b/src/cpu/pred/bpred_unit.cc
@@ -195,7 +195,8 @@
void *indirect_history = NULL;
if (inst->isUncondCtrl()) {
- DPRINTF(Branch, "[tid:%i]: Unconditional control.\n", tid);
+ DPRINTF(Branch, "[tid:%i] [sn:%i] Unconditional control\n",
+ tid,seqNum);
pred_taken = true;
// Tell the BP there was an unconditional branch.
uncondBranch(tid, pc.instAddr(), bp_history);
@@ -203,15 +204,16 @@
++condPredicted;
pred_taken = lookup(tid, pc.instAddr(), bp_history);
- DPRINTF(Branch, "[tid:%i]: [sn:%i] Branch predictor"
- " predicted %i for PC %s\n", tid, seqNum, pred_taken, pc);
+ DPRINTF(Branch, "[tid:%i] [sn:%i] Branch predictor "
+ "predicted %i for PC %s\n",
+ tid, seqNum, pred_taken, pc);
}
if (useIndirect) {
iPred.updateDirectionInfo(tid, pred_taken, indirect_history);
}
- DPRINTF(Branch, "[tid:%i]: [sn:%i] Creating prediction history "
+ DPRINTF(Branch, "[tid:%i] [sn:%i] Creating prediction history "
"for PC %s\n", tid, seqNum, pc);
PredictorHistory predict_record(seqNum, pc.instAddr(), pred_taken,
@@ -234,9 +236,9 @@
RAS[tid].pop();
- DPRINTF(Branch, "[tid:%i]: Instruction %s is a return, "
- "RAS predicted target: %s, RAS index: %i.\n",
- tid, pc, target, predict_record.RASIndex);
+ DPRINTF(Branch, "[tid:%i] [sn:%i] Instruction %s is a return, "
+ "RAS predicted target: %s, RAS index: %i\n",
+ tid, seqNum, pc, target, predict_record.RASIndex);
} else {
++BTBLookups;
@@ -248,9 +250,9 @@
// be popped off if the speculation is incorrect.
predict_record.wasCall = true;
- DPRINTF(Branch, "[tid:%i]: Instruction %s was a "
- "call, adding %s to the RAS index: %i.\n",
- tid, pc, pc, RAS[tid].topIdx());
+ DPRINTF(Branch, "[tid:%i] [sn:%i] Instruction %s was a "
+ "call, adding %s to the RAS index: %i\n",
+ tid, seqNum, pc, pc, RAS[tid].topIdx());
}
if (inst->isDirectCtrl() || !useIndirect) {
@@ -261,19 +263,19 @@
// If it's not a return, use the BTB to get target
addr.
target = BTB.lookup(pc.instAddr(), tid);
- DPRINTF(Branch, "[tid:%i]: Instruction %s predicted"
- " target is %s.\n", tid, pc, target);
+ DPRINTF(Branch, "[tid:%i] [sn:%i] Instruction %s
predicted"
+ " target is %s\n", tid,seqNum, pc, target);
} else {
- DPRINTF(Branch, "[tid:%i]: BTB doesn't have a "
- "valid entry.\n",tid);
+ DPRINTF(Branch, "[tid:%i] [sn:%i] BTB doesn't have a "
+ "valid entry\n",tid,seqNum);
pred_taken = false;
// The Direction of the branch predictor is altered
// because the BTB did not have an entry
// The predictor needs to be updated accordingly
if (!inst->isCall() && !inst->isReturn()) {
btbUpdate(tid, pc.instAddr(), bp_history);
- DPRINTF(Branch, "[tid:%i]:[sn:%i] btbUpdate"
+ DPRINTF(Branch, "[tid:%i] [sn:%i] btbUpdate"
" called for %s\n", tid, seqNum, pc);
} else if (inst->isCall() && !inst->isUncondCtrl()) {
RAS[tid].pop();
@@ -285,16 +287,18 @@
predict_record.wasIndirect = true;
++indirectLookups;
//Consult indirect predictor on indirect control
- if (iPred.lookup(pc.instAddr(), target, tid)) {
+ if (iPred.lookup(seqNum,pc.instAddr(), target, tid)) {
// Indirect predictor hit
++indirectHits;
- DPRINTF(Branch, "[tid:%i]: Instruction %s predicted "
- "indirect target is %s.\n", tid, pc, target);
+ DPRINTF(Branch, "[tid:%i] [sn:%i] "
+ "Instruction %s predicted "
+ "indirect target is %s\n", tid,seqNum, pc,
target);
} else {
++indirectMisses;
pred_taken = false;
- DPRINTF(Branch, "[tid:%i]: Instruction %s no indirect "
- "target.\n", tid, pc);
+ DPRINTF(Branch, "[tid:%i] [sn:%i] "
+ "Instruction %s no indirect "
+ "target\n", tid, seqNum,pc);
if (!inst->isCall() && !inst->isReturn()) {
} else if (inst->isCall() && !inst->isUncondCtrl()) {
@@ -319,7 +323,7 @@
predHist[tid].push_front(predict_record);
- DPRINTF(Branch, "[tid:%i]: [sn:%i]: History entry added."
+ DPRINTF(Branch, "[tid:%i] [sn:%i] History entry added."
"predHist.size(): %i\n", tid, seqNum, predHist[tid].size());
return pred_taken;
@@ -328,8 +332,8 @@
void
BPredUnit::update(const InstSeqNum &done_sn, ThreadID tid)
{
- DPRINTF(Branch, "[tid:%i]: Committing branches until "
- "[sn:%lli].\n", tid, done_sn);
+ DPRINTF(Branch, "[tid:%i] Committing branches until "
+ "[sn:%lli]\n", tid, done_sn);
while (!predHist[tid].empty() &&
predHist[tid].back().seqNum <= done_sn) {
@@ -355,16 +359,17 @@
while (!pred_hist.empty() &&
pred_hist.front().seqNum > squashed_sn) {
if (pred_hist.front().usedRAS) {
- DPRINTF(Branch, "[tid:%i]: Restoring top of RAS to: %i,"
- " target: %s.\n", tid,
+ DPRINTF(Branch, "[tid:%i] [squash sn:%i]"
+ " Restoring top of RAS to: %i,"
+ " target: %s\n", tid, squashed_sn,
pred_hist.front().RASIndex,
pred_hist.front().RASTarget);
RAS[tid].restore(pred_hist.front().RASIndex,
pred_hist.front().RASTarget);
} else if (pred_hist.front().wasCall &&
pred_hist.front().pushedRAS) {
// Was a call but predicated false. Pop RAS here
- DPRINTF(Branch, "[tid: %i] Squashing"
- " Call [sn:%i] PC: %s Popping RAS\n", tid,
+ DPRINTF(Branch, "[tid:%i] [squash sn:%i] Squashing"
+ " Call [sn:%i] PC: %s Popping RAS\n", tid,
squashed_sn,
pred_hist.front().seqNum, pred_hist.front().pc);
RAS[tid].pop();
}
@@ -375,14 +380,15 @@
iPred.deleteDirectionInfo(tid,
pred_hist.front().indirectHistory);
}
- DPRINTF(Branch, "[tid:%i]: Removing history for [sn:%i] "
- "PC %s.\n", tid, pred_hist.front().seqNum,
+ DPRINTF(Branch, "[tid:%i] [squash sn:%i] "
+ "Removing history for [sn:%i] "
+ "PC %#x\n", tid, squashed_sn, pred_hist.front().seqNum,
pred_hist.front().pc);
pred_hist.pop_front();
- DPRINTF(Branch, "[tid:%i]: predHist.size(): %i\n",
- tid, predHist[tid].size());
+ DPRINTF(Branch, "[tid:%i] [squash sn:%i] predHist.size(): %i\n",
+ tid, squashed_sn, predHist[tid].size());
}
}
@@ -407,8 +413,8 @@
++condIncorrect;
ppMisses->notify(1);
- DPRINTF(Branch, "[tid:%i]: Squashing from sequence number %i, "
- "setting target to %s.\n", tid, squashed_sn, corrTarget);
+ DPRINTF(Branch, "[tid:%i] Squashing from sequence number %i, "
+ "setting target to %s\n", tid, squashed_sn, corrTarget);
// Squash All Branches AFTER this mispredicted branch
squash(squashed_sn, tid);
@@ -433,8 +439,8 @@
if ((*hist_it).usedRAS) {
++RASIncorrect;
- DPRINTF(Branch, "[tid:%i]: Incorrect RAS [sn:%i]\n",
- tid, hist_it->seqNum);
+ DPRINTF(Branch, "[tid:%i] [squash sn:%i] Incorrect RAS
[sn:%i]\n",
+ tid, squashed_sn, hist_it->seqNum);
}
// There are separate functions for in-order and out-of-order
@@ -461,9 +467,11 @@
if (actually_taken) {
if (hist_it->wasReturn && !hist_it->usedRAS) {
- DPRINTF(Branch, "[tid: %i] Incorrectly predicted"
- " return [sn:%i] PC: %s\n", tid, hist_it->seqNum,
- hist_it->pc);
+ DPRINTF(Branch, "[tid:%i] [squash sn:%i] "
+ "Incorrectly predicted "
+ "return [sn:%i] PC: %#x\n", tid, squashed_sn,
+ hist_it->seqNum,
+ hist_it->pc);
RAS[tid].pop();
hist_it->usedRAS = true;
}
@@ -471,34 +479,38 @@
++indirectMispredicted;
iPred.recordTarget(hist_it->seqNum, corrTarget, tid);
} else {
- DPRINTF(Branch,"[tid: %i] BTB Update called for [sn:%i]"
- " PC: %s\n", tid,hist_it->seqNum, hist_it->pc);
+ DPRINTF(Branch,"[tid:%i] [squash sn:%i] "
+ "BTB Update called for [sn:%i] "
+ "PC %#x\n", tid, squashed_sn,
+ hist_it->seqNum, hist_it->pc);
BTB.update((*hist_it).pc, corrTarget, tid);
}
} else {
//Actually not Taken
if (hist_it->usedRAS) {
- DPRINTF(Branch,"[tid: %i] Incorrectly predicted"
- " return [sn:%i] PC: %s Restoring RAS\n", tid,
+ DPRINTF(Branch,"[tid:%i] [squash sn:%i] Incorrectly
predicted"
+ " return [sn:%i] PC: %#x Restoring RAS\n", tid,
+ squashed_sn,
hist_it->seqNum, hist_it->pc);
- DPRINTF(Branch, "[tid:%i]: Restoring top of RAS"
- " to: %i, target: %s.\n", tid,
+ DPRINTF(Branch, "[tid:%i] [squash sn:%i] Restoring top of
RAS"
+ " to: %i, target: %s\n", tid, squashed_sn,
hist_it->RASIndex, hist_it->RASTarget);
RAS[tid].restore(hist_it->RASIndex, hist_it->RASTarget);
hist_it->usedRAS = false;
} else if (hist_it->wasCall && hist_it->pushedRAS) {
//Was a Call but predicated false. Pop RAS here
- DPRINTF(Branch, "[tid: %i] Incorrectly predicted"
- " Call [sn:%i] PC: %s Popping RAS\n", tid,
- hist_it->seqNum, hist_it->pc);
+ DPRINTF(Branch, "[tid:%i] [squash sn:%i] "
+ "Incorrectly predicted "
+ "Call [sn:%i] PC: %s Popping RAS\n", tid,
squashed_sn,
+ hist_it->seqNum, hist_it->pc);
RAS[tid].pop();
hist_it->pushedRAS = false;
}
}
} else {
- DPRINTF(Branch, "[tid:%i]: [sn:%i] pred_hist empty, can't "
- "update.\n", tid, squashed_sn);
+ DPRINTF(Branch, "[tid:%i] [sn:%i] pred_hist empty, can't "
+ "update\n", tid, squashed_sn);
}
}
diff --git a/src/cpu/pred/indirect.cc b/src/cpu/pred/indirect.cc
index 6690abb..8c42f53 100644
--- a/src/cpu/pred/indirect.cc
+++ b/src/cpu/pred/indirect.cc
@@ -74,24 +74,26 @@
}
bool
-IndirectPredictor::lookup(Addr br_addr, TheISA::PCState& target,
- ThreadID tid)
+IndirectPredictor::lookup(InstSeqNum seq_num,
+ Addr br_addr, TheISA::PCState& target, ThreadID tid)
{
Addr set_index = getSetIndex(br_addr, threadInfo[tid].ghr, tid);
Addr tag = getTag(br_addr);
assert(set_index < numSets);
- DPRINTF(Indirect, "Looking up %x (set:%d)\n", br_addr, set_index);
+ DPRINTF(Indirect, "[sn:%i] Looking up %x (set:%d)\n",
+ seq_num, br_addr, set_index);
const auto &iset = targetCache[set_index];
for (auto way = iset.begin(); way != iset.end(); ++way) {
if (way->tag == tag) {
- DPRINTF(Indirect, "Hit %x (target:%s)\n", br_addr,
way->target);
+ DPRINTF(Indirect, "[sn:%i] Hit %x (target:%s)\n",
+ seq_num, br_addr, way->target);
target = way->target;
return true;
}
}
- DPRINTF(Indirect, "Miss %x\n", br_addr);
+ DPRINTF(Indirect, "[sn:%i] Miss %x\n",seq_num, br_addr);
return false;
}
diff --git a/src/cpu/pred/indirect.hh b/src/cpu/pred/indirect.hh
index 226a778..b32d2f7 100644
--- a/src/cpu/pred/indirect.hh
+++ b/src/cpu/pred/indirect.hh
@@ -44,7 +44,8 @@
unsigned num_sets, unsigned num_ways,
unsigned tag_bits, unsigned path_len,
unsigned inst_shift, unsigned num_threads);
- bool lookup(Addr br_addr, TheISA::PCState& br_target, ThreadID tid);
+ bool lookup(InstSeqNum seq_num, Addr br_addr,
+ TheISA::PCState& br_target, ThreadID tid);
void recordIndirect(Addr br_addr, Addr tgt_addr, InstSeqNum seq_num,
ThreadID tid);
void commit(InstSeqNum seq_num, ThreadID tid, void * indirect_history);
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I4761c49fc12b874a7d8b46779475b606865cad4b
Gerrit-Change-Number: 17248
Gerrit-PatchSet: 1
Gerrit-Owner: Andrea Mondelli <[email protected]>
Gerrit-MessageType: newchange
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