[gem5-dev] Change in gem5/gem5[master]: arch-riscv, mem: Fix for crash in riscv cpus.

[Joe Rahmeh (Gerrit)]

Joe Rahmeh has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/17349

Change subject: arch-riscv,mem: Fix for crash in riscv cpus.
......................................................................

arch-riscv,mem: Fix for crash in riscv cpus.

Running the riscv gem5 using the learning_gem5/part1/simple.y config
and the hello test:

  ./build/RISCV/gem5.debug \
  configs/learning_gem5/part1/simple.py --cmd \
  tests/test-progs/hello/bin/riscv/linux/hello \

results in an assertion failure.  Debugging the crash shows that a
packet of type swap is passed to DRAMCtrl::addToReadQueue. That packet
is marked as both read and write cuasing the assertion
      assert(! pkt->isWrite());
to fail.

Fix is to change the assertion to:
       assert(pkt->isRead());

Change-Id: I4f483d6f167141af34a1c4ab9446ff8f10d31d44
---
M src/mem/dram_ctrl.cc
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/mem/dram_ctrl.cc b/src/mem/dram_ctrl.cc
index b6ec465..d8bab82 100644
--- a/src/mem/dram_ctrl.cc
+++ b/src/mem/dram_ctrl.cc
@@ -413,7 +413,7 @@
 {
     // only add to the read queue here. whenever the request is
     // eventually done, set the readyTime, and call schedule()
-    assert(!pkt->isWrite());
+    assert(pkt->isRead());

     assert(pktCount != 0);


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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I4f483d6f167141af34a1c4ab9446ff8f10d31d44
Gerrit-Change-Number: 17349
Gerrit-PatchSet: 1
Gerrit-Owner: Joe Rahmeh <joe.rah...@gmail.com>
Gerrit-MessageType: newchange
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