Andrea Mondelli has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/17469
Change subject: dev-arm: ambiguous use of getPort()
......................................................................
dev-arm: ambiguous use of getPort()
The recent introduction of getPort() creates a conflict with
the existing method used in arm MMU.
This patch rename the old getPort() in getDMAPort() according
to the returned value (DmaPort class type)
Change-Id: Ief3d83650fd6b08490522341631244be06e380ce
---
M src/arch/arm/stage2_mmu.cc
M src/arch/arm/stage2_mmu.hh
M src/arch/arm/table_walker.cc
M src/arch/arm/tlb.cc
4 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/arch/arm/stage2_mmu.cc b/src/arch/arm/stage2_mmu.cc
index f043db2..6235c22 100644
--- a/src/arch/arm/stage2_mmu.cc
+++ b/src/arch/arm/stage2_mmu.cc
@@ -132,9 +132,9 @@
}
if (_fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) {
- parent.getPort().dmaAction(MemCmd::ReadReq, req->getPaddr(),
numBytes,
- event, data,
tc->getCpuPtr()->clockPeriod(),
- req->getFlags());
+ parent.getDMAPort().dmaAction(
+ MemCmd::ReadReq, req->getPaddr(), numBytes, event, data,
+ tc->getCpuPtr()->clockPeriod(), req->getFlags());
} else {
// We can't do the DMA access as there's been a problem, so tell
the
// event we're done
diff --git a/src/arch/arm/stage2_mmu.hh b/src/arch/arm/stage2_mmu.hh
index 8787089..69f2f52 100644
--- a/src/arch/arm/stage2_mmu.hh
+++ b/src/arch/arm/stage2_mmu.hh
@@ -110,7 +110,7 @@
* is used by the two table walkers, and is exposed externally and
* connected through the stage-one table walker.
*/
- DmaPort& getPort() { return port; }
+ DmaPort& getDMAPort() { return port; }
Fault readDataUntimed(ThreadContext *tc, Addr oVAddr, Addr descAddr,
uint8_t *data, int numBytes, Request::Flags flags, bool
isFunctional);
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index 21257de..d310e9e 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -102,7 +102,7 @@
TableWalker::setMMU(Stage2MMU *m, MasterID master_id)
{
stage2Mmu = m;
- port = &m->getPort();
+ port = &m->getDMAPort();
masterId = master_id;
}
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index dc3c35b..47c5f96 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -1246,7 +1246,7 @@
Port *
TLB::getTableWalkerPort()
{
- return &stage2Mmu->getPort();
+ return &stage2Mmu->getDMAPort();
}
void
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17469
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ief3d83650fd6b08490522341631244be06e380ce
Gerrit-Change-Number: 17469
Gerrit-PatchSet: 1
Gerrit-Owner: Andrea Mondelli <[email protected]>
Gerrit-MessageType: newchange
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
