Ryan Gambord has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/17608
Change subject: arch-arm: Fixing fallthrough and binary op errors
......................................................................
arch-arm: Fixing fallthrough and binary op errors
Recently merged patch introduced build errors on newer versions of gcc
Change-Id: I587f91b1600b68bbabcdc9bc2aa376e3c42144b7
---
M src/arch/arm/isa/formats/sve_2nd_level.isa
M src/arch/arm/isa/formats/sve_top_level.isa
M src/arch/arm/isa/insts/neon.isa
M src/arch/arm/isa/insts/neon64.isa
M src/arch/arm/isa/insts/sve.isa
5 files changed, 15 insertions(+), 4 deletions(-)
diff --git a/src/arch/arm/isa/formats/sve_2nd_level.isa
b/src/arch/arm/isa/formats/sve_2nd_level.isa
index 3c5e01c..7d10be6 100644
--- a/src/arch/arm/isa/formats/sve_2nd_level.isa
+++ b/src/arch/arm/isa/formats/sve_2nd_level.isa
@@ -118,6 +118,7 @@
return new Unknown64(machInst);
}
}
+ M5_UNREACHABLE;
}
case 0x3:
{
@@ -532,6 +533,7 @@
return new SveIndexII<int64_t>(machInst,
zd, imm5, imm5b);
}
+ M5_UNREACHABLE;
}
case 1:
{ // INDEX (scalar, immediate)
@@ -552,6 +554,7 @@
return new SveIndexRI<int64_t>(machInst,
zd, zn, imm5);
}
+ M5_UNREACHABLE;
}
case 2:
{ // INDEX (immediate, scalar)
@@ -572,6 +575,7 @@
return new SveIndexIR<int64_t>(machInst,
zd, imm5, zm);
}
+ M5_UNREACHABLE;
}
case 3:
{ // INDEX (scalars)
@@ -593,6 +597,7 @@
return new SveIndexRR<int64_t>(machInst,
zd, zn, zm);
}
+ M5_UNREACHABLE;
}
}
return new Unknown64(machInst);
diff --git a/src/arch/arm/isa/formats/sve_top_level.isa
b/src/arch/arm/isa/formats/sve_top_level.isa
index f4f1ab5..b0b1c90 100644
--- a/src/arch/arm/isa/formats/sve_top_level.isa
+++ b/src/arch/arm/isa/formats/sve_top_level.isa
@@ -127,6 +127,7 @@
case 0x3:
return decodeSveIntArithUnaryPred(machInst);
}
+ M5_UNREACHABLE;
}
}
case 0x1:
@@ -166,6 +167,7 @@
case 0x3:
return decodeSveElemCount(machInst);
}
+ M5_UNREACHABLE;
}
case 0x2:
if (bits(machInst, 20)) {
@@ -195,6 +197,7 @@
case 0x3:
return decodeSveSelVec(machInst);
}
+ M5_UNREACHABLE;
}
case 0x4:
return decodeSveIntCmpVec(machInst);
@@ -219,6 +222,7 @@
case 0x3:
return decodeSveIntWideImmUnpred(machInst);
}
+ M5_UNREACHABLE;
}
}
return new Unknown64(machInst);
@@ -279,12 +283,14 @@
case 0x3:
return decodeSveFpAccumReduc(machInst);
}
+ M5_UNREACHABLE;
}
case 0x2:
return decodeSveFpArithPred(machInst);
case 0x3:
return decodeSveFpUnaryPred(machInst);
}
+ M5_UNREACHABLE;
}
}
case 0x3:
diff --git a/src/arch/arm/isa/insts/neon.isa
b/src/arch/arm/isa/insts/neon.isa
index 1e0c116..7837a71 100644
--- a/src/arch/arm/isa/insts/neon.isa
+++ b/src/arch/arm/isa/insts/neon.isa
@@ -2050,7 +2050,7 @@
threeEqualRegInst("vand", "VandQ", "SimdAluOp", unsignedTypes, 4,
vandCode)
vbicCode = '''
- destElem = srcElem1 & ~srcElem2;
+ destElem = srcElem1 & !srcElem2;
'''
threeEqualRegInst("vbic", "VbicD", "SimdAluOp", unsignedTypes, 2,
vbicCode)
threeEqualRegInst("vbic", "VbicQ", "SimdAluOp", unsignedTypes, 4,
vbicCode)
diff --git a/src/arch/arm/isa/insts/neon64.isa
b/src/arch/arm/isa/insts/neon64.isa
index 2e0ec44..1de95b6 100644
--- a/src/arch/arm/isa/insts/neon64.isa
+++ b/src/arch/arm/isa/insts/neon64.isa
@@ -956,7 +956,7 @@
oneRegImmInstX("bic", "BicImmQX", "SimdAluOp", ("uint64_t",), 4,
bicImmCode, True)
# BIC (register)
- bicCode = "destElem = srcElem1 & ~srcElem2;"
+ bicCode = "destElem = srcElem1 & !srcElem2;"
threeEqualRegInstX("bic", "BicDX", "SimdAluOp", ("uint64_t",), 2,
bicCode)
threeEqualRegInstX("bic", "BicQX", "SimdAluOp", ("uint64_t",), 4,
bicCode)
# BIF
diff --git a/src/arch/arm/isa/insts/sve.isa b/src/arch/arm/isa/insts/sve.isa
index b1b946f..75a3c97 100644
--- a/src/arch/arm/isa/insts/sve.isa
+++ b/src/arch/arm/isa/insts/sve.isa
@@ -3178,11 +3178,11 @@
sveBinInst('asrr', 'Asrr', 'SimdAluOp', unsignedTypes, asrrCode,
PredType.MERGE, True)
# BIC (vectors, predicated)
- bicCode = 'destElem = srcElem1 & ~srcElem2;'
+ bicCode = 'destElem = srcElem1 & !srcElem2;'
sveBinInst('bic', 'BicPred', 'SimdAluOp', unsignedTypes, bicCode,
PredType.MERGE, True)
# BIC (vectors, unpredicated)
- bicCode = 'destElem = srcElem1 & ~srcElem2;'
+ bicCode = 'destElem = srcElem1 & !srcElem2;'
sveBinInst('bic', 'BicUnpred', 'SimdAluOp', unsignedTypes, bicCode)
# BIC, BICS (predicates)
svePredLogicalInst('bic', 'PredBic', 'SimdPredAluOp', ('uint8_t',),
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I587f91b1600b68bbabcdc9bc2aa376e3c42144b7
Gerrit-Change-Number: 17608
Gerrit-PatchSet: 1
Gerrit-Owner: Ryan Gambord <[email protected]>
Gerrit-MessageType: newchange
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