Hello Andreas Sandberg,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/17990
to review the following change.
Change subject: arch-arm: Trap virtual accesses to GICv3 SGI registers
......................................................................
arch-arm: Trap virtual accesses to GICv3 SGI registers
According to GICv3 documentation, a virtual write (which means
HCR.IMO/FMO = 1) to ICC_SGI0R_EL1, ICC_SGI1R_EL1, ICC_ASGI1R_EL1 should
trap to EL2.
Change-Id: Ie7a952c2ff08590bb0c6e3854df567d714c2dc94
Signed-off-by: Giacomo Travaglini <[email protected]>
Reviewed-by: Andreas Sandberg <[email protected]>
---
M src/arch/arm/insts/misc64.cc
M src/arch/arm/utility.cc
2 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc
index 7df2f76..3e7ef79 100644
--- a/src/arch/arm/insts/misc64.cc
+++ b/src/arch/arm/insts/misc64.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2013,2017-2018 ARM Limited
+ * Copyright (c) 2011-2013,2017-2019 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -38,6 +38,7 @@
*/
#include "arch/arm/insts/misc64.hh"
+#include "arch/arm/isa.hh"
std::string
ImmOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
@@ -268,6 +269,16 @@
break;
case MISCREG_IMPDEF_UNIMPL:
trap_to_hyp = hcr.tidcp && el == EL1;
+ // GICv3 regs
+ case MISCREG_ICC_SGI0R_EL1:
+ if (tc->getIsaPtr()->haveGICv3CpuIfc())
+ trap_to_hyp = hcr.fmo && el == EL1;
+ break;
+ case MISCREG_ICC_SGI1R_EL1:
+ case MISCREG_ICC_ASGI1R_EL1:
+ if (tc->getIsaPtr()->haveGICv3CpuIfc())
+ trap_to_hyp = hcr.imo && el == EL1;
+ break;
default:
break;
}
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index b41134f..2888ebb 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2009-2014, 2016-2018 ARM Limited
+ * Copyright (c) 2009-2014, 2016-2019 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -580,6 +580,16 @@
case MISCREG_PMCR:
trapToHype = hdcr.tpmcr;
break;
+ // GICv3 regs
+ case MISCREG_ICC_SGI0R:
+ if (tc->getIsaPtr()->haveGICv3CpuIfc())
+ trapToHype = hcr.fmo;
+ break;
+ case MISCREG_ICC_SGI1R:
+ case MISCREG_ICC_ASGI1R:
+ if (tc->getIsaPtr()->haveGICv3CpuIfc())
+ trapToHype = hcr.imo;
+ break;
// No default action needed
default:
break;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17990
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ie7a952c2ff08590bb0c6e3854df567d714c2dc94
Gerrit-Change-Number: 17990
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-MessageType: newchange
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