Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/18372
Change subject: mem: Remove the ISA specialized versions of port proxy's
read/write.
......................................................................
mem: Remove the ISA specialized versions of port proxy's read/write.
These selected their behavior based on ifdefs and had to be disabled
when on the NULL ISA. The versions which take an explicit endianness
have been renamed to just read/write instead of readGtoH and writeHtoG
since the direction of the translation is obvious from context.
Change-Id: I6cfbfda6c4481962d442d3370534e50532d41814
---
M src/arch/alpha/linux/system.cc
M src/arch/alpha/stacktrace.cc
M src/arch/arm/semihosting.cc
M src/arch/arm/stacktrace.cc
M src/arch/mips/stacktrace.cc
M src/arch/x86/stacktrace.cc
M src/kern/linux/helpers.cc
M src/mem/port_proxy.hh
M src/sim/aux_vector.cc
9 files changed, 58 insertions(+), 84 deletions(-)
diff --git a/src/arch/alpha/linux/system.cc b/src/arch/alpha/linux/system.cc
index 3ecf42f..33e760f 100644
--- a/src/arch/alpha/linux/system.cc
+++ b/src/arch/alpha/linux/system.cc
@@ -181,7 +181,8 @@
Tick cpuFreq = tc->getCpuPtr()->frequency();
assert(intrFreq);
FSTranslatingPortProxy &vp = tc->getVirtProxy();
- vp.writeHtoG(addr, (uint32_t)((cpuFreq / intrFreq) * 0.9988));
+ vp.write(addr, (uint32_t)((cpuFreq / intrFreq) * 0.9988),
+ GuestByteOrder);
}
}
diff --git a/src/arch/alpha/stacktrace.cc b/src/arch/alpha/stacktrace.cc
index 3c302d2..dfe7474 100644
--- a/src/arch/alpha/stacktrace.cc
+++ b/src/arch/alpha/stacktrace.cc
@@ -54,23 +54,23 @@
if (!symtab->findAddress("thread_info_size", addr))
panic("thread info not compiled into kernel\n");
- thread_info_size = vp.readGtoH<int32_t>(addr);
+ thread_info_size = vp.read<int32_t>(addr, GuestByteOrder);
if (!symtab->findAddress("task_struct_size", addr))
panic("thread info not compiled into kernel\n");
- task_struct_size = vp.readGtoH<int32_t>(addr);
+ task_struct_size = vp.read<int32_t>(addr, GuestByteOrder);
if (!symtab->findAddress("thread_info_task", addr))
panic("thread info not compiled into kernel\n");
- task_off = vp.readGtoH<int32_t>(addr);
+ task_off = vp.read<int32_t>(addr, GuestByteOrder);
if (!symtab->findAddress("task_struct_pid", addr))
panic("thread info not compiled into kernel\n");
- pid_off = vp.readGtoH<int32_t>(addr);
+ pid_off = vp.read<int32_t>(addr, GuestByteOrder);
if (!symtab->findAddress("task_struct_comm", addr))
panic("thread info not compiled into kernel\n");
- name_off = vp.readGtoH<int32_t>(addr);
+ name_off = vp.read<int32_t>(addr, GuestByteOrder);
}
Addr
@@ -83,7 +83,7 @@
Addr tsk;
FSTranslatingPortProxy &vp = tc->getVirtProxy();
- tsk = vp.readGtoH<Addr>(base + task_off);
+ tsk = vp.read<Addr>(base + task_off, GuestByteOrder);
return tsk;
}
@@ -98,7 +98,7 @@
uint16_t pd;
FSTranslatingPortProxy &vp = tc->getVirtProxy();
- pd = vp.readGtoH<uint16_t>(task + pid_off);
+ pd = vp.read<uint16_t>(task + pid_off, GuestByteOrder);
return pd;
}
diff --git a/src/arch/arm/semihosting.cc b/src/arch/arm/semihosting.cc
index 51107cb..3f9c095 100644
--- a/src/arch/arm/semihosting.cc
+++ b/src/arch/arm/semihosting.cc
@@ -176,7 +176,7 @@
DPRINTF(Semihosting, "Semihosting call64: %s(0x%x)\n", call->name,
param);
argv[0] = param;
for (int i = 0; i < call->argc64; ++i) {
- argv[i + 1] = proxy.readGtoH<uint64_t>(param + i * 8, endian);
+ argv[i + 1] = proxy.read<uint64_t>(param + i * 8, endian);
DPRINTF(Semihosting, "\t: 0x%x\n", argv[i + 1]);
}
@@ -211,7 +211,7 @@
DPRINTF(Semihosting, "Semihosting call32: %s(0x%x)\n", call->name,
param);
argv[0] = param;
for (int i = 0; i < call->argc32; ++i) {
- argv[i + 1] = proxy.readGtoH<uint32_t>(param + i * 4, endian);
+ argv[i + 1] = proxy.read<uint32_t>(param + i * 4, endian);
DPRINTF(Semihosting, "\t: 0x%x\n", argv[i + 1]);
}
@@ -556,9 +556,9 @@
(const uint8_t *)cmdLine.c_str(), cmdLine.size() + 1);
if (aarch64)
- proxy.writeHtoG<uint64_t>(argv[0] + 1 * 8, cmdLine.size(),
endian);
+ proxy.write<uint64_t>(argv[0] + 1 * 8, cmdLine.size(), endian);
else
- proxy.writeHtoG<uint32_t>(argv[0] + 1 * 4, cmdLine.size(),
endian);
+ proxy.write<uint32_t>(argv[0] + 1 * 4, cmdLine.size(), endian);
return retOK(0);
} else {
return retError(0);
@@ -609,15 +609,15 @@
PortProxy &proxy = physProxy(tc);
ByteOrder endian = ArmISA::byteOrder(tc);
if (aarch64) {
- proxy.writeHtoG<uint64_t>(base + 0 * 8, heap_base, endian);
- proxy.writeHtoG<uint64_t>(base + 1 * 8, heap_limit, endian);
- proxy.writeHtoG<uint64_t>(base + 2 * 8, stack_base, endian);
- proxy.writeHtoG<uint64_t>(base + 3 * 8, stack_limit, endian);
+ proxy.write<uint64_t>(base + 0 * 8, heap_base, endian);
+ proxy.write<uint64_t>(base + 1 * 8, heap_limit, endian);
+ proxy.write<uint64_t>(base + 2 * 8, stack_base, endian);
+ proxy.write<uint64_t>(base + 3 * 8, stack_limit, endian);
} else {
- proxy.writeHtoG<uint32_t>(base + 0 * 4, heap_base, endian);
- proxy.writeHtoG<uint32_t>(base + 1 * 4, heap_limit, endian);
- proxy.writeHtoG<uint32_t>(base + 2 * 4, stack_base, endian);
- proxy.writeHtoG<uint32_t>(base + 3 * 4, stack_limit, endian);
+ proxy.write<uint32_t>(base + 0 * 4, heap_base, endian);
+ proxy.write<uint32_t>(base + 1 * 4, heap_limit, endian);
+ proxy.write<uint32_t>(base + 2 * 4, stack_base, endian);
+ proxy.write<uint32_t>(base + 3 * 4, stack_limit, endian);
}
return retOK(0);
@@ -666,10 +666,10 @@
const uint64_t tick = semiTick(curTick());
if (aarch64) {
- proxy.writeHtoG<uint64_t>(argv[0], tick, endian);
+ proxy.write<uint64_t>(argv[0], tick, endian);
} else {
- proxy.writeHtoG<uint32_t>(argv[0] + 0 * 4, tick, endian);
- proxy.writeHtoG<uint32_t>(argv[0] + 1 * 4, tick >> 32, endian);
+ proxy.write<uint32_t>(argv[0] + 0 * 4, tick, endian);
+ proxy.write<uint32_t>(argv[0] + 1 * 4, tick >> 32, endian);
}
return retOK(0);
diff --git a/src/arch/arm/stacktrace.cc b/src/arch/arm/stacktrace.cc
index de57775..b4dbf72 100644
--- a/src/arch/arm/stacktrace.cc
+++ b/src/arch/arm/stacktrace.cc
@@ -54,7 +54,7 @@
if (!symtab->findAddress(name, addr))
panic("thread info not compiled into kernel\n");
- return vp.readGtoH<int32_t>(addr);
+ return vp.read<int32_t>(addr, GuestByteOrder);
}
ProcessInfo::ProcessInfo(ThreadContext *_tc) : tc(_tc)
@@ -76,7 +76,7 @@
Addr tsk;
FSTranslatingPortProxy &vp = tc->getVirtProxy();
- tsk = vp.readGtoH<Addr>(base + task_off);
+ tsk = vp.read<Addr>(base + task_off, GuestByteOrder);
return tsk;
}
@@ -91,7 +91,7 @@
uint16_t pd;
FSTranslatingPortProxy &vp = tc->getVirtProxy();
- pd = vp.readGtoH<uint16_t>(task + pid_off);
+ pd = vp.read<uint16_t>(task + pid_off, GuestByteOrder);
return pd;
}
diff --git a/src/arch/mips/stacktrace.cc b/src/arch/mips/stacktrace.cc
index f584855..da492f1 100644
--- a/src/arch/mips/stacktrace.cc
+++ b/src/arch/mips/stacktrace.cc
@@ -41,7 +41,6 @@
#include "mem/fs_translating_port_proxy.hh"
#include "sim/system.hh"
-using namespace std;
using namespace MipsISA;
ProcessInfo::ProcessInfo(ThreadContext *_tc) : tc(_tc)
@@ -57,7 +56,7 @@
Addr tsk;
FSTranslatingPortProxy &vp = tc->getVirtProxy();
- tsk = vp.readGtoH<Addr>(base + task_off);
+ tsk = vp.read<Addr>(base + task_off, GuestByteOrder);
return tsk;
}
@@ -72,12 +71,12 @@
uint16_t pd;
FSTranslatingPortProxy &vp = tc->getVirtProxy();
- pd = vp.readGtoH<uint16_t>(task + pid_off);
+ pd = vp.read<uint16_t>(task + pid_off, GuestByteOrder);
return pd;
}
-string
+std::string
ProcessInfo::name(Addr ksp) const
{
Addr task = this->task(ksp);
diff --git a/src/arch/x86/stacktrace.cc b/src/arch/x86/stacktrace.cc
index cdfd64b..2d9eaea 100644
--- a/src/arch/x86/stacktrace.cc
+++ b/src/arch/x86/stacktrace.cc
@@ -54,7 +54,7 @@
if (!symtab->findAddress(name, addr))
panic("thread info not compiled into kernel\n");
- return vp.readGtoH<int32_t>(addr);
+ return vp.read<int32_t>(addr, GuestByteOrder);
}
ProcessInfo::ProcessInfo(ThreadContext *_tc) : tc(_tc)
@@ -76,7 +76,7 @@
Addr tsk;
FSTranslatingPortProxy &vp = tc->getVirtProxy();
- tsk = vp.readGtoH<Addr>(base + task_off);
+ tsk = vp.read<Addr>(base + task_off, GuestByteOrder);
return tsk;
}
@@ -91,7 +91,7 @@
uint16_t pd;
FSTranslatingPortProxy &vp = tc->getVirtProxy();
- pd = vp.readGtoH<uint16_t>(task + pid_off);
+ pd = vp.read<uint16_t>(task + pid_off, GuestByteOrder);
return pd;
}
diff --git a/src/kern/linux/helpers.cc b/src/kern/linux/helpers.cc
index 54fc421..ed58427 100644
--- a/src/kern/linux/helpers.cc
+++ b/src/kern/linux/helpers.cc
@@ -43,6 +43,7 @@
#include "config/the_isa.hh"
#include "cpu/thread_context.hh"
#include "mem/fs_translating_port_proxy.hh"
+#include "sim/byteswap.hh"
#include "sim/system.hh"
struct DmesgEntry {
@@ -107,9 +108,12 @@
return;
}
- uint32_t log_buf_len = proxy.readGtoH<uint32_t>(addr_lb_len);
- uint32_t log_first_idx = proxy.readGtoH<uint32_t>(addr_first);
- uint32_t log_next_idx = proxy.readGtoH<uint32_t>(addr_next);
+ uint32_t log_buf_len =
+ proxy.read<uint32_t>(addr_lb_len, TheISA::GuestByteOrder);
+ uint32_t log_first_idx =
+ proxy.read<uint32_t>(addr_first, TheISA::GuestByteOrder);
+ uint32_t log_next_idx =
+ proxy.read<uint32_t>(addr_next, TheISA::GuestByteOrder);
if (log_first_idx >= log_buf_len || log_next_idx >= log_buf_len) {
warn("dmesg pointers/length corrupted\n");
diff --git a/src/mem/port_proxy.hh b/src/mem/port_proxy.hh
index fe87bf5..fcc21f6 100644
--- a/src/mem/port_proxy.hh
+++ b/src/mem/port_proxy.hh
@@ -59,11 +59,6 @@
#ifndef __MEM_PORT_PROXY_HH__
#define __MEM_PORT_PROXY_HH__
-#include "config/the_isa.hh"
-#if THE_ISA != NULL_ISA
- #include "arch/isa_traits.hh"
-#endif
-
#include "mem/port.hh"
#include "sim/byteswap.hh"
@@ -93,27 +88,34 @@
public:
PortProxy(MasterPort &port, unsigned int cacheLineSize) :
- _port(port), _cacheLineSize(cacheLineSize) { }
+ _port(port), _cacheLineSize(cacheLineSize)
+ {}
virtual ~PortProxy() { }
/**
* Read size bytes memory at address and store in p.
*/
- virtual void readBlob(Addr addr, uint8_t* p, int size) const {
+ virtual void
+ readBlob(Addr addr, uint8_t* p, int size) const
+ {
readBlobPhys(addr, 0, p, size);
}
/**
* Write size bytes from p to address.
*/
- virtual void writeBlob(Addr addr, const uint8_t* p, int size) const {
+ virtual void
+ writeBlob(Addr addr, const uint8_t* p, int size) const
+ {
writeBlobPhys(addr, 0, p, size);
}
/**
* Fill size bytes starting at addr with byte value val.
*/
- virtual void memsetBlob(Addr addr, uint8_t v, int size) const {
+ virtual void
+ memsetBlob(Addr addr, uint8_t v, int size) const
+ {
memsetBlobPhys(addr, 0, v, size);
}
@@ -152,30 +154,14 @@
* Performs selected endianness transform.
*/
template <typename T>
- T readGtoH(Addr address, ByteOrder guest_byte_order) const;
+ T read(Addr address, ByteOrder guest_byte_order) const;
/**
* Write object T to address. Writes sizeof(T) bytes.
* Performs selected endianness transform.
*/
template <typename T>
- void writeHtoG(Addr address, T data, ByteOrder guest_byte_order) const;
-
-#if THE_ISA != NULL_ISA
- /**
- * Read sizeof(T) bytes from address and return as object T.
- * Performs Guest to Host endianness transform.
- */
- template <typename T>
- T readGtoH(Addr address) const;
-
- /**
- * Write object T to address. Writes sizeof(T) bytes.
- * Performs Host to Guest endianness transform.
- */
- template <typename T>
- void writeHtoG(Addr address, T data) const;
-#endif
+ void write(Addr address, T data, ByteOrder guest_byte_order) const;
};
@@ -214,7 +200,7 @@
template <typename T>
T
-PortProxy::readGtoH(Addr address, ByteOrder byte_order) const
+PortProxy::read(Addr address, ByteOrder byte_order) const
{
T data;
readBlob(address, (uint8_t*)&data, sizeof(T));
@@ -223,29 +209,10 @@
template <typename T>
void
-PortProxy::writeHtoG(Addr address, T data, ByteOrder byte_order) const
+PortProxy::write(Addr address, T data, ByteOrder byte_order) const
{
data = htog(data, byte_order);
writeBlob(address, (uint8_t*)&data, sizeof(T));
}
-#if THE_ISA != NULL_ISA
-template <typename T>
-T
-PortProxy::readGtoH(Addr address) const
-{
- T data;
- readBlob(address, (uint8_t*)&data, sizeof(T));
- return TheISA::gtoh(data);
-}
-
-template <typename T>
-void
-PortProxy::writeHtoG(Addr address, T data) const
-{
- data = TheISA::htog(data);
- writeBlob(address, (uint8_t*)&data, sizeof(T));
-}
-#endif
-
#endif // __MEM_PORT_PROXY_HH__
diff --git a/src/sim/aux_vector.cc b/src/sim/aux_vector.cc
index 87a22e4..18834ac 100644
--- a/src/sim/aux_vector.cc
+++ b/src/sim/aux_vector.cc
@@ -66,6 +66,9 @@
#error "THE_ISA not set"
#endif
+#include "arch/isa_traits.hh"
+#include "sim/byteswap.hh"
+
template<class IntType>
AuxVector<IntType>::AuxVector(IntType type, IntType val)
: _auxType(TheISA::htog(type)), _auxVal(TheISA::htog(val)),
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I6cfbfda6c4481962d442d3370534e50532d41814
Gerrit-Change-Number: 18372
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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