Hello Andreas Sandberg,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/18388
to review the following change.
Change subject: arch-arm: Correct target EL field in TLBI operations
......................................................................
arch-arm: Correct target EL field in TLBI operations
Some TLB Invalidation operations affecting the EL2 translation regime
were marked as targeting EL1 instead of EL2
Change-Id: I77821eec7a409e9df6a6814855f9a375832ffe74
Signed-off-by: Giacomo Travaglini <[email protected]>
Reviewed-by: Jan-Peter Larsson <[email protected]>
Reviewed-by: Andreas Sandberg <[email protected]>
---
M src/arch/arm/isa.cc
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 42e1cba..d5d88e6 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -1219,7 +1219,7 @@
assert32(tc);
scr = readMiscReg(MISCREG_SCR, tc);
- TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
+ TLBIMVAA tlbiOp(EL2, haveSecurity && !scr.ns,
mbits(newVal, 31,12), true);
tlbiOp(tc);
@@ -1232,7 +1232,7 @@
assert32(tc);
scr = readMiscReg(MISCREG_SCR, tc);
- TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
+ TLBIMVAA tlbiOp(EL2, haveSecurity && !scr.ns,
mbits(newVal, 31,12), true);
tlbiOp.broadcast(tc);
@@ -1347,7 +1347,7 @@
{
assert32(tc);
- TLBIALLN tlbiOp(EL1, true);
+ TLBIALLN tlbiOp(EL2, true);
tlbiOp(tc);
return;
}
@@ -1356,7 +1356,7 @@
{
assert32(tc);
- TLBIALLN tlbiOp(EL1, true);
+ TLBIALLN tlbiOp(EL2, true);
tlbiOp.broadcast(tc);
return;
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I77821eec7a409e9df6a6814855f9a375832ffe74
Gerrit-Change-Number: 18388
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-MessageType: newchange
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