Gabe Black has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/18434

Change subject: cpu: alpha: Delete all occurrances of the simPalCheck function.
......................................................................

cpu: alpha: Delete all occurrances of the simPalCheck function.

This is now handled within the ISA description.

Change-Id: Ie409bb46d102e59d4eb41408d9196fe235626d32
---
M src/arch/alpha/ev5.cc
M src/cpu/checker/cpu.hh
M src/cpu/exec_context.hh
M src/cpu/minor/exec_context.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/cpu.hh
M src/cpu/o3/dyn_inst.hh
M src/cpu/o3/dyn_inst_impl.hh
M src/cpu/simple/exec_context.hh
M src/cpu/simple_thread.cc
M src/cpu/simple_thread.hh
11 files changed, 0 insertions(+), 116 deletions(-)



diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index 8b7691a..a847cd5 100644
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -479,32 +479,3 @@
 }

 } // namespace AlphaISA
-
-using namespace AlphaISA;
-
-/**
- * Check for special simulator handling of specific PAL calls.
- * If return value is false, actual PAL call will be suppressed.
- */
-bool
-SimpleThread::simPalCheck(int palFunc)
-{
-    if (kernelStats)
-        kernelStats->callpal(palFunc, this);
-
-    switch (palFunc) {
-      case PAL::halt:
-        halt();
-        if (--System::numSystemsRunning == 0)
-            exitSimLoop("all cpus halted");
-        break;
-
-      case PAL::bpt:
-      case PAL::bugchk:
-        if (system->breakpoint())
-            return false;
-        break;
-    }
-
-    return true;
-}
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 3f374e8..f70545b 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -554,8 +554,6 @@
     void setStCondFailures(unsigned int sc_failures) override {}
     /////////////////////////////////////////////////////

-    bool simPalCheck(int palFunc) override
-    { return thread->simPalCheck(palFunc); }
     void wakeup(ThreadID tid) override { }
     // Assume that the normal CPU's call to syscall was successful.
     // The checker's state would have already been updated by the syscall.
diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh
index e2c6dd6..2c70eb4 100644
--- a/src/cpu/exec_context.hh
+++ b/src/cpu/exec_context.hh
@@ -311,19 +311,6 @@

     /**
      * @{
-     * @name Alpha-Specific Interfaces
-     */
-
-    /**
-     * Check for special simulator handling of specific PAL calls.  If
-     * return value is false, actual PAL call will be suppressed.
-     */
-    virtual bool simPalCheck(int palFunc) = 0;
-
-    /** @} */
-
-    /**
-     * @{
      * @name ARM-Specific Interfaces
      */

diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh
index 22c6432..414bb41 100644
--- a/src/cpu/minor/exec_context.hh
+++ b/src/cpu/minor/exec_context.hh
@@ -365,16 +365,6 @@
         return thread.setMiscReg(reg.index(), val);
     }

-    bool
-    simPalCheck(int palFunc) override
-    {
-#if THE_ISA == ALPHA_ISA
-        return thread.simPalCheck(palFunc);
-#else
-        return false;
-#endif
-    }
-
     void
     syscall(int64_t callnum, Fault *fault) override
     {
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index bec4244..50de81b 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -918,32 +918,6 @@
 }

 template <class Impl>
-bool
-FullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid)
-{
-#if THE_ISA == ALPHA_ISA
-    if (this->thread[tid]->kernelStats)
-        this->thread[tid]->kernelStats->callpal(palFunc,
-                                                this->threadContexts[tid]);
-
-    switch (palFunc) {
-      case PAL::halt:
-        halt();
-        if (--System::numSystemsRunning == 0)
-            exitSimLoop("all cpus halted");
-        break;
-
-      case PAL::bpt:
-      case PAL::bugchk:
-        if (this->system->breakpoint())
-            return false;
-        break;
-    }
-#endif
-    return true;
-}
-
-template <class Impl>
 void
 FullO3CPU<Impl>::switchRenameMode(ThreadID tid, UnifiedFreeList* freelist)
 {
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 11b5f18..49cec54 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -386,8 +386,6 @@
     /** Traps to handle given fault. */
     void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst);

-    bool simPalCheck(int palFunc, ThreadID tid);
-
     /** Check if a change in renaming is needed for vector registers.
      * The vecMode variable is updated and propagated to rename maps.
      *
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 6bb8e2d..0d7877a 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -250,7 +250,6 @@
     }
     /** Traps to handle specified fault. */
     void trap(const Fault &fault);
-    bool simPalCheck(int palFunc) override;

     /** Emulates a syscall. */
     void syscall(int64_t callnum, Fault *fault) override;
diff --git a/src/cpu/o3/dyn_inst_impl.hh b/src/cpu/o3/dyn_inst_impl.hh
index 5fb5973..fbeb3c2 100644
--- a/src/cpu/o3/dyn_inst_impl.hh
+++ b/src/cpu/o3/dyn_inst_impl.hh
@@ -192,16 +192,6 @@
 }

 template <class Impl>
-bool
-BaseO3DynInst<Impl>::simPalCheck(int palFunc)
-{
-#if THE_ISA != ALPHA_ISA
-    panic("simPalCheck called, but PAL only exists in Alpha!\n");
-#endif
-    return this->cpu->simPalCheck(palFunc, this->threadNumber);
-}
-
-template <class Impl>
 void
 BaseO3DynInst<Impl>::syscall(int64_t callnum, Fault *fault)
 {
diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh
index fa6c17f..34b38b7 100644
--- a/src/cpu/simple/exec_context.hh
+++ b/src/cpu/simple/exec_context.hh
@@ -502,16 +502,6 @@
     /** Returns a pointer to the ThreadContext. */
     ThreadContext *tcBase() override { return thread->getTC(); }

-    /**
-     * Check for special simulator handling of specific PAL calls.  If
-     * return value is false, actual PAL call will be suppressed.
-     */
-    bool
-    simPalCheck(int palFunc) override
-    {
-        return thread->simPalCheck(palFunc);
-    }
-
     bool
     readPredicate() const override
     {
diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc
index b676b04..9067e87 100644
--- a/src/cpu/simple_thread.cc
+++ b/src/cpu/simple_thread.cc
@@ -212,14 +212,3 @@
 {
     TheISA::copyRegs(src_tc, this);
 }
-
-// The following methods are defined in src/arch/alpha/ev5.cc for
-// Alpha.
-#if THE_ISA != ALPHA_ISA
-
-bool
-SimpleThread::simPalCheck(int palFunc)
-{
-    return true;
-}
-#endif
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index d74bd11..b8d0c4e 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -183,8 +183,6 @@

     void dumpFuncProfile() override;

-    bool simPalCheck(int palFunc);
-
     /*******************************************
      * ThreadContext interface functions.
      ******************************************/

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ie409bb46d102e59d4eb41408d9196fe235626d32
Gerrit-Change-Number: 18434
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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