Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/18550
Change subject: arm: Switch over how the SVE vector length is retrieved.
......................................................................
arm: Switch over how the SVE vector length is retrieved.
Instructions should, unless otherwise unavoidable, use the ExecContext
to retrieve values and not poke through to the ThreadContext. This
also shortens up the call sights since they don't have to extract the
ThreadContext from the ExecContext.
Change-Id: I88d5f0049f2a6552273cfb68651e72100d43b078
---
M src/arch/arm/insts/static_inst.cc
M src/arch/arm/insts/static_inst.hh
M src/arch/arm/isa/insts/fp64.isa
M src/arch/arm/isa/insts/ldr64.isa
M src/arch/arm/isa/insts/neon64.isa
M src/arch/arm/isa/insts/neon64_mem.isa
M src/arch/arm/isa/insts/sve.isa
7 files changed, 64 insertions(+), 118 deletions(-)
diff --git a/src/arch/arm/insts/static_inst.cc
b/src/arch/arm/insts/static_inst.cc
index cc0e8f3..52c0097 100644
--- a/src/arch/arm/insts/static_inst.cc
+++ b/src/arch/arm/insts/static_inst.cc
@@ -1161,9 +1161,9 @@
}
unsigned
-ArmStaticInst::getCurSveVecLenInBits(ThreadContext *tc)
+ArmStaticInst::getCurSveVecLenInBits(ExecContext *xc)
{
- return tc->getIsaPtr()->getCurSveVecLenInBits(tc);
+ return xc->readMiscReg(MISCREG_SVE_VEC_LEN_BITS);
}
}
diff --git a/src/arch/arm/insts/static_inst.hh
b/src/arch/arm/insts/static_inst.hh
index 9caf016..50720ea 100644
--- a/src/arch/arm/insts/static_inst.hh
+++ b/src/arch/arm/insts/static_inst.hh
@@ -541,19 +541,19 @@
return simpleAsBytes(buf, max_size, machInst);
}
- static unsigned getCurSveVecLenInBits(ThreadContext *tc);
+ static unsigned getCurSveVecLenInBits(ExecContext *xc);
static unsigned
- getCurSveVecLenInQWords(ThreadContext *tc)
+ getCurSveVecLenInQWords(ExecContext *xc)
{
- return getCurSveVecLenInBits(tc) >> 6;
+ return getCurSveVecLenInBits(xc) >> 6;
}
template<typename T>
static unsigned
- getCurSveVecLen(ThreadContext *tc)
+ getCurSveVecLen(ExecContext *xc)
{
- return getCurSveVecLenInBits(tc) / (8 * sizeof(T));
+ return getCurSveVecLenInBits(xc) / (8 * sizeof(T));
}
};
}
diff --git a/src/arch/arm/isa/insts/fp64.isa
b/src/arch/arm/isa/insts/fp64.isa
index 7decbac..42850da 100644
--- a/src/arch/arm/isa/insts/fp64.isa
+++ b/src/arch/arm/isa/insts/fp64.isa
@@ -46,7 +46,7 @@
zeroSveVecRegUpperPartCode = '''
ArmISA::ISA::zeroSveVecRegUpperPart(%s,
- ArmStaticInst::getCurSveVecLen<uint64_t>(xc->tcBase()));
+ ArmStaticInst::getCurSveVecLen<uint64_t>(xc));
'''
fmovImmSCode = vfp64EnabledCheckCode + '''
diff --git a/src/arch/arm/isa/insts/ldr64.isa
b/src/arch/arm/isa/insts/ldr64.isa
index 56112a7..b1a023a 100644
--- a/src/arch/arm/isa/insts/ldr64.isa
+++ b/src/arch/arm/isa/insts/ldr64.isa
@@ -186,8 +186,7 @@
elif self.flavor == "fp":
accEpilogCode = '''
ArmISA::ISA::zeroSveVecRegUpperPart(AA64FpDest,
- ArmStaticInst::getCurSveVecLen<uint64_t>(
- xc->tcBase()));
+ ArmStaticInst::getCurSveVecLen<uint64_t>(xc));
'''
if self.size in (1, 2, 4):
accCode = '''
@@ -240,11 +239,9 @@
if self.flavor == "fp":
accEpilogCode = '''
ArmISA::ISA::zeroSveVecRegUpperPart(AA64FpDest,
- ArmStaticInst::getCurSveVecLen<uint64_t>(
- xc->tcBase()));
+ ArmStaticInst::getCurSveVecLen<uint64_t>(xc));
ArmISA::ISA::zeroSveVecRegUpperPart(AA64FpDest2,
- ArmStaticInst::getCurSveVecLen<uint64_t>(
- xc->tcBase()));
+ ArmStaticInst::getCurSveVecLen<uint64_t>(xc));
'''
if self.size == 4:
accCode = '''
diff --git a/src/arch/arm/isa/insts/neon64.isa
b/src/arch/arm/isa/insts/neon64.isa
index 2e0ec44..cac8c69 100644
--- a/src/arch/arm/isa/insts/neon64.isa
+++ b/src/arch/arm/isa/insts/neon64.isa
@@ -50,7 +50,7 @@
zeroSveVecRegUpperPartCode = '''
TheISA::ISA::zeroSveVecRegUpperPart(%s,
- ArmStaticInst::getCurSveVecLen<uint64_t>(xc->tcBase()));
+ ArmStaticInst::getCurSveVecLen<uint64_t>(xc));
'''
def threeEqualRegInstX(name, Name, opClass, types, rCount, op,
diff --git a/src/arch/arm/isa/insts/neon64_mem.isa
b/src/arch/arm/isa/insts/neon64_mem.isa
index 03ad294..6d4c562 100644
--- a/src/arch/arm/isa/insts/neon64_mem.isa
+++ b/src/arch/arm/isa/insts/neon64_mem.isa
@@ -46,7 +46,7 @@
zeroSveVecRegUpperPartCode = '''
ArmISA::ISA::zeroSveVecRegUpperPart(%s,
- ArmStaticInst::getCurSveVecLen<uint64_t>(xc->tcBase()));
+ ArmStaticInst::getCurSveVecLen<uint64_t>(xc));
'''
def mkMemAccMicroOp(name):
diff --git a/src/arch/arm/isa/insts/sve.isa b/src/arch/arm/isa/insts/sve.isa
index c46a34d..9a161c6 100644
--- a/src/arch/arm/isa/insts/sve.isa
+++ b/src/arch/arm/isa/insts/sve.isa
@@ -1256,8 +1256,7 @@
def sveAdrInst(name, Name, opClass, types, op):
global header_output, exec_output, decoders
code = sveEnabledCheckCode + '''
- unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
- xc->tcBase());
+ unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(xc);
for (unsigned i = 0; i < eCount; i++) {
const Element& srcElem1 = AA64FpOp1_x[i];
Element srcElem2 = AA64FpOp2_x[i];
@@ -1285,8 +1284,7 @@
else:
srcType = 'uint64_t' if srcSize == SrcSize.Src64bit
else 'uint32_t'
code = sveEnabledCheckCode + '''
- unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
- xc->tcBase());
+ unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(xc);
%(stype)s srcElem1 = static_cast<%(stype)s>(XOp1);
%(stype)s srcElem2 = static_cast<%(stype)s>(XOp2);
bool cond, first = false, none = true, last = true;
@@ -1344,8 +1342,7 @@
assert not (destType == DestType.Vector and
srcSize != SrcSize.Src64bit)
code = sveEnabledCheckCode + '''
- unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
- xc->tcBase());
+ unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(xc);
int count = 0;
for (unsigned i = 0; i < eCount; i++) {
if (GpOp_x[i]) {
@@ -1376,8 +1373,7 @@
def svePredCountPredInst(name, Name, opClass, types):
global header_output, exec_output, decoders
code = sveEnabledCheckCode + '''
- unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
- xc->tcBase());
+ unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(xc);
int count = 0;
for (unsigned i = 0; i < eCount; i++) {
if (POp1_x[i] && GpOp_x[i]) {
@@ -1398,8 +1394,7 @@
def sveIndex(fmt):
global header_output, exec_output, decoders
code = sveEnabledCheckCode + '''
- unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
- xc->tcBase());'''
+ unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(xc);'''
if fmt == IndexFormat.ImmReg or fmt == IndexFormat.ImmImm:
code += '''
const Element& srcElem1 = imm1;'''
@@ -1437,8 +1432,7 @@
predType=PredType.NONE, decoder='Generic'):
global header_output, exec_output, decoders
code = sveEnabledCheckCode + '''
- unsigned eCount = ArmStaticInst::getCurSveVecLen<DElement>(
- xc->tcBase());
+ unsigned eCount = ArmStaticInst::getCurSveVecLen<DElement>(xc);
for (unsigned i = 0; i < eCount; i++) {
SElement srcElem1 = AA64FpOp1_xd[i];
DElement destElem = 0;'''
@@ -1480,8 +1474,7 @@
else 'XOp1' if srcRegType == SrcRegType.Scalar
else 'AA64FpOp1_x[0]')
code = sveEnabledCheckCode + '''
- unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
- xc->tcBase());
+ unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(xc);
for (unsigned i = 0; i < eCount; i++) {
Element srcElem1 = %s;
Element destElem = 0;''' % op1
@@ -1521,8 +1514,7 @@
decoder='Generic'):
global header_output, exec_output, decoders
code = sveEnabledCheckCode + '''
- unsigned eCount = ArmStaticInst::getCurSveVecLen<%(bigElemType)s>(
- xc->tcBase());
+ unsigned eCount =
ArmStaticInst::getCurSveVecLen<%(bigElemType)s>(xc);
for (unsigned i = 0; i < eCount; i++) {
SElement srcElem1 = AA64FpOp1_x%(bigElemSuffix)s[i] &
mask(sizeof(SElement) * 8);
@@ -1553,8 +1545,7 @@
decoder='Generic'):
global header_output, exec_output, decoders
code = sveEnabledCheckCode + '''
- unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
- xc->tcBase());
+ unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(xc);
ArmISA::VecRegContainer tmpVecC;
auto auxOp1 = tmpVecC.as<Element>();
for (unsigned i = 0; i < eCount; ++i) {
@@ -1584,10 +1575,8 @@
decoder='Generic'):
global header_output, exec_output, decoders
code = sveEnabledCheckCode + '''
- unsigned eCount = ArmStaticInst::getCurSveVecLen<SElement>(
- xc->tcBase());
- unsigned eWideCount = ArmStaticInst::getCurSveVecLen<DElement>(
- xc->tcBase());
+ unsigned eCount = ArmStaticInst::getCurSveVecLen<SElement>(xc);
+ unsigned eWideCount = ArmStaticInst::getCurSveVecLen<DElement>(xc);
DElement destElem = %(identity)s;
for (unsigned i = 0; i < eCount; i++) {
if (GpOp_xs[i]) {
@@ -1614,8 +1603,7 @@
decoder='Generic'):
global header_output, exec_output, decoders
code = sveEnabledCheckCode + '''
- unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
- xc->tcBase());
+ unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(xc);
ArmISA::VecRegContainer tmpVecC;
auto tmpVec = tmpVecC.as<Element>();
int ePow2Count = 1;
@@ -1663,8 +1651,7 @@
decoder='Generic'):
global header_output, exec_output, decoders
code = sveEnabledCheckCode + '''
- unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
- xc->tcBase());
+ unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(xc);
for (unsigned i = 0; i < eCount; i++) {'''
if predType != PredType.NONE:
code += '''
@@ -1711,8 +1698,7 @@
isUnary=False, decoder='Generic'):
global header_output, exec_output, decoders
code = sveEnabledCheckCode + '''
- unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
- xc->tcBase());
+ unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(xc);
for (unsigned i = 0; i < eCount; i++) {'''
# TODO: handle unsigned-to-signed conversion properly...
if isUnary:
@@ -1759,8 +1745,7 @@
predType=PredType.NONE, decoder='Generic'):
global header_output, exec_output, decoders
code = sveEnabledCheckCode + '''
- unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
- xc->tcBase());
+ unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(xc);
ArmISA::VecRegContainer tmpVecC;
auto auxOp2 = tmpVecC.as<Element>();
for (unsigned i = 0; i < eCount; i++) {
@@ -1811,8 +1796,7 @@
def sveBinIdxInst(name, Name, opClass, types, op, decoder='Generic'):
global header_output, exec_output, decoders
code = sveEnabledCheckCode + '''
- unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
- xc->tcBase());
+ unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(xc);
// Number of elements in a 128 bit segment
constexpr unsigned ePerSegment = 128 / sizeof(Element);
@@ -1855,8 +1839,7 @@
isDestructive)
global header_output, exec_output, decoders
code = sveEnabledCheckCode + '''
- unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
- xc->tcBase());'''
+ unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(xc);'''
if customIterCode is None:
code += '''
for (unsigned i = 0; i < eCount; i++) {'''
@@ -1915,8 +1898,7 @@
global header_output, exec_output, decoders
assert predType in (PredType.ZERO, PredType.SELECT)
code = sveEnabledCheckCode + '''
- unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
- xc->tcBase());
+ unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(xc);
ArmISA::VecPredRegContainer tmpPredC;
auto auxGpOp = tmpPredC.as<Element>();
for (unsigned i = 0; i < eCount; i++) {
@@ -1959,8 +1941,7 @@
decoder='Generic'):
global header_output, exec_output, decoders
code = sveEnabledCheckCode + '''
- unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
- xc->tcBase());'''
+ unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(xc);'''
code += iterCode
iop = InstObjParams(name, 'Sve' + Name, 'SvePredBinPermOp',
{'code': code, 'op_class': opClass}, [])
@@ -1979,8 +1960,7 @@
extraPrologCode = '''
auto& destPred = PDest;'''
code = sveEnabledCheckCode + '''
- unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
- xc->tcBase());
+ unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(xc);
ArmISA::VecPredRegContainer tmpPredC;
auto tmpPred = tmpPredC.as<Element>();
for (unsigned i = 0; i < eCount; ++i)
@@ -2019,8 +1999,7 @@
def sveTerInst(name, Name, opClass, types, op, decoder='Generic'):
global header_output, exec_output, decoders
code = sveEnabledCheckCode + '''
- unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
- xc->tcBase());
+ unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(xc);
for (unsigned i = 0; i < eCount; i++) {
const Element& srcElem1 = AA64FpOp1_x[i];
const Element& srcElem2 = AA64FpOp2_x[i];
@@ -2043,8 +2022,7 @@
def sveTerIdxInst(name, Name, opClass, types, op, decoder='Generic'):
global header_output, exec_output, decoders
code = sveEnabledCheckCode + '''
- unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
- xc->tcBase());
+ unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(xc);
// Number of elements in a 128 bit segment
constexpr unsigned ePerSegment = 128 / sizeof(Element);
@@ -2077,8 +2055,7 @@
def sveTerImmInst(name, Name, opClass, types, op, decoder='Generic'):
global header_output, exec_output, decoders
code = sveEnabledCheckCode + '''
- unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
- xc->tcBase());
+ unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(xc);
for (unsigned i = 0; i < eCount; i++) {
const Element& srcElem2 = AA64FpOp2_x[i];
Element srcElem3 = imm;
@@ -2102,8 +2079,7 @@
extraPrologCode = '''
auto& destPred = PDest;'''
code = sveEnabledCheckCode + '''
- unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
- xc->tcBase());
+ unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(xc);
unsigned predCount = sveDecodePredCount(imm, eCount);
destPred.reset();
for (unsigned i = 0; i < eCount; i++) {
@@ -2138,8 +2114,7 @@
extraPrologCode = '''
auto& destPred = PDest;'''
code = sveEnabledCheckCode + '''
- unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
- xc->tcBase());
+ unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(xc);
ArmISA::VecPredRegContainer tmpPredC;
auto tmpPred = tmpPredC.as<Element>();
for (unsigned i = 0; i < eCount; ++i)
@@ -2183,8 +2158,7 @@
extraPrologCode = '''
auto& destPred = PDest;'''
code = sveEnabledCheckCode + '''
- unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
- xc->tcBase());
+ unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(xc);
ArmISA::VecPredRegContainer tmpPredC;
auto tmpPred = tmpPredC.as<Element>();
for (unsigned i = 0; i < eCount; ++i)
@@ -2219,8 +2193,7 @@
dstAcc = True, decoder = 'Generic'):
global header_output, exec_output, decoders
code = sveEnabledCheckCode + '''
- unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
- xc->tcBase());
+ unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(xc);
unsigned count = sveDecodePredCount(pattern, eCount);
'''
if destType == DestType.Vector:
@@ -2265,8 +2238,7 @@
decoder = 'Generic'):
global header_output, exec_output, decoders
code = sveEnabledCheckCode + '''
- unsigned eCount = ArmStaticInst::getCurSveVecLen<uint8_t>(
- xc->tcBase());
+ unsigned eCount = ArmStaticInst::getCurSveVecLen<uint8_t>(xc);
bool dobreak = false;
ArmISA::VecPredRegContainer tmpPredC;
auto auxGpOp = tmpPredC.as<uint8_t>();
@@ -2317,8 +2289,7 @@
decoder = 'Generic'):
global header_output, exec_output, decoders
code = sveEnabledCheckCode + '''
- unsigned eCount = ArmStaticInst::getCurSveVecLen<uint8_t>(
- xc->tcBase());
+ unsigned eCount = ArmStaticInst::getCurSveVecLen<uint8_t>(xc);
bool last = POp1_ub.lastActive(GpOp_ub, eCount);
ArmISA::VecPredRegContainer tmpPredC;
auto auxGpOp = tmpPredC.as<uint8_t>();
@@ -2359,8 +2330,7 @@
decoder = 'Generic'):
global header_output, exec_output, decoders
code = sveEnabledCheckCode + '''
- unsigned eCount = ArmStaticInst::getCurSveVecLen<uint8_t>(
- xc->tcBase());
+ unsigned eCount = ArmStaticInst::getCurSveVecLen<uint8_t>(xc);
bool last = POp1_ub.lastActive(GpOp_ub, eCount);
for (unsigned i = 0; i < eCount; i++) {
if (!last) {
@@ -2394,8 +2364,7 @@
destType = DstRegType.Scalar, decoder = 'Generic'):
global header_output, exec_output, decoders
code = sveEnabledCheckCode + '''
- unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
- xc->tcBase());
+ unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(xc);
int last;
for (last = eCount - 1; last >= 0; --last) {
if (GpOp_x[last]) {
@@ -2456,8 +2425,7 @@
def svePNextInst(name, Name, opClass, types, decoder = 'Generic'):
global header_output, exec_output, decoders
code = sveEnabledCheckCode + '''
- unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
- xc->tcBase());
+ unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(xc);
ArmISA::VecPredRegContainer tmpPredC;
auto auxGpOp = tmpPredC.as<Element>();
for (unsigned i = 0; i < eCount; ++i) {
@@ -2498,8 +2466,7 @@
def svePFirstInst(name, Name, opClass, decoder = 'Generic'):
global header_output, exec_output, decoders
code = sveEnabledCheckCode + '''
- unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
- xc->tcBase());
+ unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(xc);
ArmISA::VecPredRegContainer tmpPredC;
auto auxGpOp = tmpPredC.as<Element>();
for (unsigned i = 0; i < eCount; ++i)
@@ -2535,8 +2502,7 @@
def sveTblInst(name, Name, opClass, decoder = 'Generic'):
global header_output, exec_output, decoders
code = sveEnabledCheckCode + '''
- unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
- xc->tcBase());
+ unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(xc);
for (int i = 0; i < eCount; ++i) {
Element idx = AA64FpOp2_x[i];
Element val;
@@ -2563,8 +2529,7 @@
extraPrologCode = '''
auto& destPred = PDest;'''
code = sveEnabledCheckCode + '''
- unsigned eCount = ArmStaticInst::getCurSveVecLen<DElement>(
- xc->tcBase());'''
+ unsigned eCount = ArmStaticInst::getCurSveVecLen<DElement>(xc);'''
if unpackHalf == Unpack.Low:
if regType == SrcRegType.Predicate:
code += '''
@@ -2619,8 +2584,7 @@
def svePredTestInst(name, Name, opClass, decoder = 'Generic'):
global header_output, exec_output, decoders
code = sveEnabledCheckCode + '''
- unsigned eCount = ArmStaticInst::getCurSveVecLen<uint8_t>(
- xc->tcBase());
+ unsigned eCount = ArmStaticInst::getCurSveVecLen<uint8_t>(xc);
CondCodesNZ = (POp1_ub.firstActive(GpOp_ub, eCount) << 1) |
POp1_ub.noneActive(GpOp_ub, eCount);
CondCodesC = !POp1_ub.lastActive(GpOp_ub, eCount);
@@ -2634,8 +2598,7 @@
def sveCompactInst(name, Name, opClass, types, decoder = 'Generic'):
global header_output, exec_output, decoders
code = sveEnabledCheckCode + '''
- unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
- xc->tcBase());
+ unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(xc);
ArmISA::VecRegContainer tmpVecC;
auto auxOp1 = tmpVecC.as<Element>();
for (unsigned i = 0; i < eCount; ++i) {
@@ -2705,8 +2668,7 @@
def sveExtInst(name, Name, opClass, decoder = 'Generic'):
global header_output, exec_output, decoders
code = sveEnabledCheckCode + '''
- unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
- xc->tcBase());
+ unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(xc);
ArmISA::VecRegContainer tmpVecC;
auto auxOp1 = tmpVecC.as<Element>();
for (unsigned i = 0; i < eCount; ++i) {
@@ -2734,8 +2696,7 @@
def sveSpliceInst(name, Name, opClass, types, decoder = 'Generic'):
global header_output, exec_output, decoders
code = sveEnabledCheckCode + '''
- unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
- xc->tcBase());
+ unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(xc);
ArmISA::VecRegContainer tmpVecC;
auto auxDest = tmpVecC.as<Element>();
int firstelem = -1, lastelem = -2;
@@ -2770,8 +2731,7 @@
def sveDupIndexInst(name, Name, opClass, types, decoder = 'Generic'):
global header_output, exec_output, decoders
code = sveEnabledCheckCode + '''
- unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
- xc->tcBase());
+ unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(xc);
Element srcElem1 = 0;
if (imm < eCount) {
srcElem1 = AA64FpOp1_x[imm];
@@ -2795,8 +2755,7 @@
extraPrologCode = '''
auto& destPred = PDest;'''
code = sveEnabledCheckCode + '''
- unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
- xc->tcBase());'''
+ unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(xc);'''
if srcType == SrcRegType.Predicate:
code += '''
ArmISA::VecPredRegContainer tmpPredC;
@@ -2839,8 +2798,7 @@
assert srcType in (SrcRegType.SimdFpScalar, SrcRegType.Scalar)
global header_output, exec_output, decoders
code = sveEnabledCheckCode + '''
- unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
- xc->tcBase());'''
+ unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(xc);'''
if srcType == SrcRegType.Scalar:
code += '''
auto& srcElem1 = XOp1;'''
@@ -2866,8 +2824,7 @@
def sveDotInst(name, Name, opClass, types, isIndexed = True):
global header_output, exec_output, decoders
code = sveEnabledCheckCode + '''
- unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
- xc->tcBase());
+ unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(xc);
for (int i = 0; i < eCount; ++i) {'''
if isIndexed:
code += '''
@@ -2907,8 +2864,7 @@
decoder = 'Generic'):
global header_output, exec_output, decoders
code = sveEnabledCheckCode + '''
- unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
- xc->tcBase());'''
+ unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(xc);'''
code += '''
Element destElem = AA64FpDestMerge_x[0];
for (int i = 0; i < eCount; ++i) {
@@ -2935,8 +2891,7 @@
decoder = 'Generic'):
global header_output, exec_output, decoders
code = sveEnabledCheckCode + '''
- unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
- xc->tcBase());'''
+ unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(xc);'''
code += '''
bool sub_i = (rot == 1);
bool sub_r = (rot == 3);
@@ -2983,8 +2938,7 @@
assert predType in (PredType.NONE, PredType.MERGE)
global header_output, exec_output, decoders
code = sveEnabledCheckCode + '''
- unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
- xc->tcBase());'''
+ unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(xc);'''
code += '''
uint32_t sel_a = rot & 0x1;
uint32_t sel_b = sel_a ? 0 : 1;
@@ -3083,8 +3037,7 @@
sveBinInst('add', 'AddUnpred', 'SimdAddOp', unsignedTypes, addCode)
# ADDPL
addvlCode = sveEnabledCheckCode + '''
- unsigned eCount = ArmStaticInst::getCurSveVecLen<uint%d_t>(
- xc->tcBase());
+ unsigned eCount = ArmStaticInst::getCurSveVecLen<uint%d_t>(xc);
XDest = XOp1 + eCount * (int64_t) imm;
'''
buildXImmDataInst('addpl', addvlCode % 64, buildCc=False)
@@ -4048,8 +4001,7 @@
predType=PredType.MERGE, srcRegType=SrcRegType.Vector)
# RDFFR (unpredicated)
rdffrUnpredCode = '''
- unsigned eCount = ArmStaticInst::getCurSveVecLen<uint8_t>(
- xc->tcBase());
+ unsigned eCount = ArmStaticInst::getCurSveVecLen<uint8_t>(xc);
for (unsigned i = 0; i < eCount; i++) {
PDest_ub[i] = Ffr_ub[i];
}'''
@@ -4057,8 +4009,7 @@
rdffrUnpredCode)
# RDFFR, RDFFRS (predicated)
rdffrPredCode = '''
- unsigned eCount = ArmStaticInst::getCurSveVecLen<uint8_t>(
- xc->tcBase());
+ unsigned eCount = ArmStaticInst::getCurSveVecLen<uint8_t>(xc);
for (unsigned i = 0; i < eCount; i++) {
if (GpOp_ub[i]) {
PDest_ub[i] = Ffr_ub[i];
@@ -4072,8 +4023,7 @@
rdffrPredCode, PredType.ZERO, True)
# RDVL
rdvlCode = sveEnabledCheckCode + '''
- unsigned eCount = ArmStaticInst::getCurSveVecLen<uint8_t>(
- xc->tcBase());
+ unsigned eCount = ArmStaticInst::getCurSveVecLen<uint8_t>(xc);
XDest = eCount * (int64_t) imm;
'''
rdvlIop = InstObjParams('rdvl', 'SveRdvl', 'RegImmOp', rdvlCode, [])
@@ -4755,8 +4705,7 @@
whileLTCode, SrcSize.Src64bit)
# WRFFR
wrffrCode = '''
- unsigned eCount = ArmStaticInst::getCurSveVecLen<uint8_t>(
- xc->tcBase());
+ unsigned eCount = ArmStaticInst::getCurSveVecLen<uint8_t>(xc);
for (unsigned i = 0; i < eCount; i++) {
Ffr_ub[i] = POp1_ub[i];
}'''
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18550
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I88d5f0049f2a6552273cfb68651e72100d43b078
Gerrit-Change-Number: 18550
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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