Giacomo Travaglini has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/18598 )
Change subject: dev-arm: Read correct version of ICC_BPR register
......................................................................
dev-arm: Read correct version of ICC_BPR register
Some methods like groupPriorityMask check for the value of binary point
registers. Those registers have a minimum value. Writing to those
register is taking this into account, but the problem with the minimum
value arises when the value is checked before sw is writing to them.
In this case the minimum value won't be considered if the read is
directly forwarded to the ISA class.
Change-Id: Id432a37f1634b02bc478d65c52ffb88323d4bb77
Signed-off-by: Giacomo Travaglini <[email protected]>
Reviewed-by: Andreas Sandberg <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18598
Maintainer: Andreas Sandberg <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/dev/arm/gic_v3_cpu_interface.cc
M src/dev/arm/gic_v3_cpu_interface.hh
2 files changed, 11 insertions(+), 6 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/dev/arm/gic_v3_cpu_interface.cc
b/src/dev/arm/gic_v3_cpu_interface.cc
index 3598f34..4a0a8e3 100644
--- a/src/dev/arm/gic_v3_cpu_interface.cc
+++ b/src/dev/arm/gic_v3_cpu_interface.cc
@@ -36,6 +36,9 @@
#include "dev/arm/gic_v3_distributor.hh"
#include "dev/arm/gic_v3_redistributor.hh"
+const uint8_t Gicv3CPUInterface::GIC_MIN_BPR;
+const uint8_t Gicv3CPUInterface::GIC_MIN_BPR_NS;
+
Gicv3CPUInterface::Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id)
: BaseISADevice(),
gic(gic),
@@ -322,6 +325,8 @@
bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1);
} else {
bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR1_EL1);
+ bpr = std::max(bpr, group == Gicv3::G1S ?
+ GIC_MIN_BPR : GIC_MIN_BPR_NS);
}
if (sat_inc) {
@@ -1844,7 +1849,7 @@
* GroupBits() Pseudocode from spec.
*/
uint32_t
-Gicv3CPUInterface::groupPriorityMask(Gicv3::GroupId group) const
+Gicv3CPUInterface::groupPriorityMask(Gicv3::GroupId group)
{
ICC_CTLR_EL1 icc_ctlr_el1_s =
isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
@@ -1859,9 +1864,9 @@
int bpr;
if (group == Gicv3::G0S) {
- bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR0_EL1) & 0x7;
+ bpr = readMiscReg(MISCREG_ICC_BPR0_EL1) & 0x7;
} else {
- bpr = isa->readMiscRegNoEffect(MISCREG_ICC_BPR1_EL1) & 0x7;
+ bpr = readMiscReg(MISCREG_ICC_BPR1_EL1) & 0x7;
}
if (group == Gicv3::G1NS) {
@@ -2165,7 +2170,7 @@
}
bool
-Gicv3CPUInterface::hppiCanPreempt() const
+Gicv3CPUInterface::hppiCanPreempt()
{
if (hppi.prio == 0xff) {
// there is no pending interrupt
diff --git a/src/dev/arm/gic_v3_cpu_interface.hh
b/src/dev/arm/gic_v3_cpu_interface.hh
index 931eb1d..e6dcb51 100644
--- a/src/dev/arm/gic_v3_cpu_interface.hh
+++ b/src/dev/arm/gic_v3_cpu_interface.hh
@@ -296,11 +296,11 @@
uint32_t getHPPIR1() const;
int getHPPVILR() const;
bool groupEnabled(Gicv3::GroupId group) const;
- uint32_t groupPriorityMask(Gicv3::GroupId group) const;
+ uint32_t groupPriorityMask(Gicv3::GroupId group);
bool haveEL(ArmISA::ExceptionLevel el) const;
int highestActiveGroup() const;
uint8_t highestActivePriority() const;
- bool hppiCanPreempt() const;
+ bool hppiCanPreempt();
bool hppviCanPreempt(int lrIdx) const;
bool inSecureState() const;
ArmISA::InterruptTypes intSignalType(Gicv3::GroupId group) const;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Id432a37f1634b02bc478d65c52ffb88323d4bb77
Gerrit-Change-Number: 18598
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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