Giacomo Gabrielli has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/13522 )
Change subject: arch-arm: Treat SVE prefetch instructions as no-ops
......................................................................
arch-arm: Treat SVE prefetch instructions as no-ops
Change-Id: Ife0424e274dd65d6dc4f6e5cc5e37d17b03be0d8
Signed-off-by: Giacomo Gabrielli <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13522
Tested-by: kokoro <[email protected]>
Reviewed-by: Andreas Sandberg <[email protected]>
Maintainer: Andreas Sandberg <[email protected]>
---
M src/arch/arm/isa/formats/sve_2nd_level.isa
1 file changed, 10 insertions(+), 6 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/isa/formats/sve_2nd_level.isa
b/src/arch/arm/isa/formats/sve_2nd_level.isa
index 7b2d3af..d4e7528 100644
--- a/src/arch/arm/isa/formats/sve_2nd_level.isa
+++ b/src/arch/arm/isa/formats/sve_2nd_level.isa
@@ -2930,11 +2930,11 @@
uint8_t b14_13 = bits(machInst, 14, 13);
if (b14_13 == 0x2 && bits(machInst, 4) == 0) {
// TODO: SVE contiguous prefetch (scalar plus
scalar)
- return new Unknown64(machInst);
+ return new WarnUnimplemented("prf[bhwd]",
machInst);
} else if (b14_13 == 0x3 && bits(machInst, 4) == 0) {
// TODO: SVE 32-bit gather prefetch (vector plus
// immediate)
- return new Unknown64(machInst);
+ return new WarnUnimplemented("prf[bhwd]",
machInst);
}
}
}
@@ -2963,7 +2963,7 @@
case 0x0:
if (bits(machInst, 21) && bits(machInst, 4) == 0) {
// TODO: SVE 32-bit gather prefetch (vector plus
immediate)
- break;
+ return new WarnUnimplemented("prf[bhwd]", machInst);
}
break;
case 0x1:
@@ -3040,6 +3040,10 @@
uint64_t imm = sext<9>((bits(machInst, 21, 16) << 3) |
bits(machInst, 12, 10));
return new SveLdrVec(machInst, zt, rn, imm);
+ } else if (bits(machInst, 22) == 1 &&
+ bits(machInst, 4) == 0) {
+ // TODO: SVE contiguous prefetch (scalar plus
immediate)
+ return new WarnUnimplemented("prf[bhwd]", machInst);
}
break;
}
@@ -3210,7 +3214,7 @@
} else {
if (bits(machInst, 14, 13) == 0x3 && bits(machInst, 4) ==
0) {
// TODO: SVE 64-bit gather prefetch (vector plus
immediate)
- break;
+ return new WarnUnimplemented("prf[bhwd]", machInst);
}
}
break;
@@ -3237,7 +3241,7 @@
} else if (bits(machInst, 4) == 0) {
// TODO: SVE 64-bit gather prefetch (scalar plus unpacked
// 32-bit scaled offsets)
- return new Unknown64(machInst);
+ return new WarnUnimplemented("prf[bhwd]", machInst);
}
break;
case 0x3:
@@ -3280,7 +3284,7 @@
} else if (bits(machInst, 4) == 0) {
// TODO: SVE 64-bit gather prefetch (scalar plus 64-bit
// scaled offsets)
- break;
+ return new WarnUnimplemented("prf[bhwd]", machInst);
}
}
break;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ife0424e274dd65d6dc4f6e5cc5e37d17b03be0d8
Gerrit-Change-Number: 13522
Gerrit-PatchSet: 11
Gerrit-Owner: Giacomo Gabrielli <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Giacomo Gabrielli <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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