Giacomo Gabrielli has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/13525 )
Change subject: cpu-o3: Increase LSQ buffer sizes to match max vector length
......................................................................
cpu-o3: Increase LSQ buffer sizes to match max vector length
Change-Id: I5890c7cfa147125ce3389001f85d56d4b5a9911d
Signed-off-by: Gabor Dozsa <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13525
Tested-by: kokoro <[email protected]>
Maintainer: Andreas Sandberg <[email protected]>
Reviewed-by: Michael LeBeane <[email protected]>
Reviewed-by: Jason Lowe-Power <[email protected]>
---
M src/cpu/o3/lsq_unit.hh
1 file changed, 8 insertions(+), 5 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Michael LeBeane: Looks good to me, approved
Andreas Sandberg: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index 5c64971..d3f1d07 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -51,6 +51,7 @@
#include <queue>
#include "arch/generic/debugfaults.hh"
+#include "arch/generic/vec_reg.hh"
#include "arch/isa_traits.hh"
#include "arch/locked_mem.hh"
#include "arch/mmapped_ipr.hh"
@@ -80,6 +81,8 @@
class LSQUnit
{
public:
+ static constexpr auto MaxDataBytes = MaxVecRegLenInBytes;
+
typedef typename Impl::O3CPU O3CPU;
typedef typename Impl::DynInstPtr DynInstPtr;
typedef typename Impl::CPUPol::IEW IEW;
@@ -97,7 +100,7 @@
/** The request. */
LSQRequest* req;
/** The size of the operation. */
- uint8_t _size;
+ uint32_t _size;
/** Valid entry. */
bool _valid;
public:
@@ -142,8 +145,8 @@
/** Member accessors. */
/** @{ */
bool valid() const { return _valid; }
- uint8_t& size() { return _size; }
- const uint8_t& size() const { return _size; }
+ uint32_t& size() { return _size; }
+ const uint32_t& size() const { return _size; }
const DynInstPtr& instruction() const { return inst; }
/** @} */
};
@@ -152,7 +155,7 @@
{
private:
/** The store data. */
- char _data[64]; // TODO: 64 should become a parameter
+ char _data[MaxDataBytes];
/** Whether or not the store can writeback. */
bool _canWB;
/** Whether or not the store is committed. */
@@ -659,7 +662,7 @@
if (req->mainRequest()->isMmappedIpr()) {
assert(!load_inst->memData);
- load_inst->memData = new uint8_t[64];
+ load_inst->memData = new uint8_t[MaxDataBytes];
ThreadContext *thread = cpu->tcBase(lsqID);
PacketPtr main_pkt = new Packet(req->mainRequest(),
MemCmd::ReadReq);
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I5890c7cfa147125ce3389001f85d56d4b5a9911d
Gerrit-Change-Number: 13525
Gerrit-PatchSet: 10
Gerrit-Owner: Giacomo Gabrielli <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Gabor Dozsa <[email protected]>
Gerrit-Reviewer: Giacomo Gabrielli <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: Michael LeBeane <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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