Hello Gabor Dozsa,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/19172
to review the following change.
Change subject: arch-arm: Fix reg dependency for SVE gather microops
......................................................................
arch-arm: Fix reg dependency for SVE gather microops
The first microop of an SVE gather creates a copy of the
source vecreg into AA64FpUreg0. The subsequent microops
must refer to this copy as a source in order to establish
the correct register dependencies.
Change-Id: I84d8c331f9f9ebca609948a15f686a7cde67dc31
Signed-off-by: Gabor Dozsa <[email protected]>
Reviewed-by: Giacomo Gabrielli <[email protected]>
---
M src/arch/arm/isa/insts/sve_mem.isa
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/src/arch/arm/isa/insts/sve_mem.isa
b/src/arch/arm/isa/insts/sve_mem.isa
index 0fc74b7..c88de38 100644
--- a/src/arch/arm/isa/insts/sve_mem.isa
+++ b/src/arch/arm/isa/insts/sve_mem.isa
@@ -1,4 +1,4 @@
-// Copyright (c) 2017-2018 ARM Limited
+// Copyright (c) 2017-2019 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -1117,11 +1117,12 @@
tplHeader = 'template <class RegElemType, class MemElemType>'
tplArgs = '<RegElemType, MemElemType>'
if indexed_addr_form == IndexedAddrForm.VEC_PLUS_IMM:
- eaCode = '''
+ eaCode_store = '''
EA = AA64FpBase_x[elemIndex] + imm * sizeof(MemElemType)'''
+ eaCode_load = '''
+ EA = AA64FpUreg0_x[elemIndex] + imm * sizeof(MemElemType)'''
else:
- eaCode = '''
- uint64_t offset = AA64FpOffset_x[elemIndex];
+ offset_code = '''
if (offsetIs32) {
offset &= (1ULL << 32) - 1;
}
@@ -1132,6 +1133,11 @@
offset *= sizeof(MemElemType);
}
EA = XBase + offset'''
+ eaCode_store = '''
+ uint64_t offset = AA64FpOffset_x[elemIndex];''' + offset_code
+ eaCode_load = '''
+ uint64_t offset = AA64FpUreg0_x[elemIndex];''' + offset_code
+
loadMemAccCode = '''
AA64FpDest_x[elemIndex] = memData;
'''
@@ -1149,7 +1155,7 @@
{'tpl_header': tplHeader,
'tpl_args': tplArgs,
'memacc_code': loadMemAccCode,
- 'ea_code' : sveEnabledCheckCode + eaCode,
+ 'ea_code' : sveEnabledCheckCode + eaCode_load,
'fault_status_set_code' : faultStatusSetCode,
'fault_status_reset_code' : faultStatusResetCode,
'pred_check_code' : predCheckCode,
@@ -1163,7 +1169,7 @@
{'tpl_header': tplHeader,
'tpl_args': tplArgs,
'memacc_code': storeMemAccCode,
- 'ea_code' : sveEnabledCheckCode + eaCode,
+ 'ea_code' : sveEnabledCheckCode + eaCode_store,
'pred_check_code' : predCheckCode,
'fa_code' : ''},
['IsMicroop', 'IsMemRef', 'IsStore'])
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/19172
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I84d8c331f9f9ebca609948a15f686a7cde67dc31
Gerrit-Change-Number: 19172
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Gabrielli <[email protected]>
Gerrit-Reviewer: Gabor Dozsa <[email protected]>
Gerrit-MessageType: newchange
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