Hello Ciro Santilli,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/19229
to review the following change.
Change subject: dev-arm: Reapply GICv3 changes that were lost during
refactoring
......................................................................
dev-arm: Reapply GICv3 changes that were lost during refactoring
The GICv3 code refactoring performed by:
https://gem5-review.googlesource.com/c/public/gem5/+/16484
reverted the following patches
https://gem5-review.googlesource.com/c/public/gem5/+/16544
https://gem5-review.googlesource.com/c/public/gem5/+/16545/3
This commit is reintroducing them
Change-Id: I2c875c11570ed66ec9203449446faca3864c64d6
Signed-off-by: Giacomo Travaglini <[email protected]>
Reviewed-by: Ciro Santilli <[email protected]>
---
M src/dev/arm/gic_v3_cpu_interface.cc
1 file changed, 36 insertions(+), 4 deletions(-)
diff --git a/src/dev/arm/gic_v3_cpu_interface.cc
b/src/dev/arm/gic_v3_cpu_interface.cc
index 4a0a8e3..3488193 100644
--- a/src/dev/arm/gic_v3_cpu_interface.cc
+++ b/src/dev/arm/gic_v3_cpu_interface.cc
@@ -159,22 +159,36 @@
case MISCREG_ICC_IGRPEN0:
case MISCREG_ICC_IGRPEN0_EL1: {
if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
- return isa->readMiscRegNoEffect(MISCREG_ICV_IGRPEN0_EL1);
+ return readMiscReg(MISCREG_ICV_IGRPEN0_EL1);
}
break;
}
+ case MISCREG_ICV_IGRPEN0_EL1: {
+ ICH_VMCR_EL2 ich_vmcr_el2 =
+ isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
+ value = ich_vmcr_el2.VENG0;
+ break;
+ }
+
// Interrupt Group 1 Enable register EL1
case MISCREG_ICC_IGRPEN1:
case MISCREG_ICC_IGRPEN1_EL1: {
if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
- return isa->readMiscRegNoEffect(MISCREG_ICV_IGRPEN1_EL1);
+ return readMiscReg(MISCREG_ICV_IGRPEN1_EL1);
}
break;
}
+ case MISCREG_ICV_IGRPEN1_EL1: {
+ ICH_VMCR_EL2 ich_vmcr_el2 =
+ isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
+ value = ich_vmcr_el2.VENG1;
+ break;
+ }
+
// Interrupt Group 1 Enable register EL3
case MISCREG_ICC_MGRPEN1:
case MISCREG_ICC_IGRPEN1_EL3:
@@ -380,7 +394,7 @@
case MISCREG_ICC_PMR:
case MISCREG_ICC_PMR_EL1:
if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo))
{
- return isa->readMiscRegNoEffect(MISCREG_ICV_PMR_EL1);
+ return readMiscReg(MISCREG_ICV_PMR_EL1);
}
if (haveEL(EL3) && !inSecureState() &&
@@ -401,6 +415,14 @@
break;
+ case MISCREG_ICV_PMR_EL1: { // Priority Mask Register
+ ICH_VMCR_EL2 ich_vmcr_el2 =
+ isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
+
+ value = ich_vmcr_el2.VPMR;
+ break;
+ }
+
// Interrupt Acknowledge Register 0
case MISCREG_ICC_IAR0:
case MISCREG_ICC_IAR0_EL1: {
@@ -1273,7 +1295,7 @@
case MISCREG_ICC_PMR:
case MISCREG_ICC_PMR_EL1: {
if ((currEL() == EL1) && !inSecureState() && (hcr_imo ||
hcr_fmo)) {
- return isa->setMiscRegNoEffect(MISCREG_ICV_PMR_EL1, val);
+ return setMiscReg(MISCREG_ICV_PMR_EL1, val);
}
val &= 0xff;
@@ -1303,6 +1325,16 @@
break;
}
+ case MISCREG_ICV_PMR_EL1: { // Priority Mask Register
+ ICH_VMCR_EL2 ich_vmcr_el2 =
+ isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
+ ich_vmcr_el2.VPMR = val & 0xff;
+
+ isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
+ virtualUpdate();
+ return;
+ }
+
// Interrupt Group 0 Enable Register EL1
case MISCREG_ICC_IGRPEN0:
case MISCREG_ICC_IGRPEN0_EL1: {
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I2c875c11570ed66ec9203449446faca3864c64d6
Gerrit-Change-Number: 19229
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Ciro Santilli <[email protected]>
Gerrit-MessageType: newchange
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