YIFEI LIU has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/20108 )

Change subject: arch-riscv: Update Page Table Entry
......................................................................

arch-riscv: Update Page Table Entry

This patch updates the structure of Page Table Entry (PTE) in Gem5
with respect to Risc-V Privileged Architecuture V1.10 Chapter 4.3.
The old PTE variables are kept to pass the compliation but will be
removed the future patch.

Change-Id: Ie7a17a6bf3fab36c9d1b9bc9b04f7b53a8b6b5cb
---
M src/arch/riscv/pagetable.hh
1 file changed, 17 insertions(+), 2 deletions(-)



diff --git a/src/arch/riscv/pagetable.hh b/src/arch/riscv/pagetable.hh
index 249d032..9e196c5 100644
--- a/src/arch/riscv/pagetable.hh
+++ b/src/arch/riscv/pagetable.hh
@@ -51,7 +51,7 @@
     Addr VPN;
     uint8_t asid;

-    bool G;
+

     /* Contents of Entry Lo0 */
     Addr PFN0;  // Physical Frame Number - Even
@@ -65,6 +65,21 @@
     bool V1;    // Odd entry Valid Bit
     uint8_t C1; // Cache Coherency Bits (3 bits)

+    // RV39 page table entry
+    // according to RISC-V Privileged Architectures V1.10 Chapter 4.3
+    Addr PPN2;  // PPN Level-2, bit width: 26
+    Addr PPN1;  // PPN Level-1, bit width: 9
+    Addr PPN0;  // PPN Level-0, bit width: 9
+    uint8_t RSW;// Reserved for supervisor software, bit width: 2
+    bool D;     // PTE dirty bit
+    bool A;     // PTE accessed bit
+    bool G;     // PTE global mapping bit
+    bool U;     // PTE user mode accessible bit
+    bool X;     // PTE permission bit, check Table 4.4
+    bool W;     // PTE permission bit, check Table 4.4
+    bool R;     // PTE permission bit, check Table 4.4
+    bool V;     // PTE valid bit
+
     /*
      * The next few variables are put in as optimizations to reduce
      * TLB lookup overheads. For a given Mask, what is the address shift
@@ -73,7 +88,7 @@
     int AddrShiftAmount;
     int OffsetMask;

-    bool Valid() { return (V0 | V1); };
+    bool Valid() { return (V); };
     void serialize(CheckpointOut &cp) const;
     void unserialize(CheckpointIn &cp);
 };

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ie7a17a6bf3fab36c9d1b9bc9b04f7b53a8b6b5cb
Gerrit-Change-Number: 20108
Gerrit-PatchSet: 1
Gerrit-Owner: YIFEI LIU <liu.ad2...@gmail.com>
Gerrit-MessageType: newchange
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