Ian Jiang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/22563 )
Change subject: RISCV: Fix immediate decoding for integer shift immediate
instructions
......................................................................
RISCV: Fix immediate decoding for integer shift immediate instructions
The "shamt" in integer shift immediate instructions is an unsigned immediate
encoded in bits[25:20]. While the original Gem5 uses bits[31:20] as an
int64_t.
This patch fixes the problem by adding for these instructions a new format
IShiftOp in which the immediate type is changed to uint64_t and is masked to
keep the last (lower) 6 bits.
The instructions affected include:
- Shift Left Logical Immediate, slli
- Shift Right Logical Immediate, srli
- Shift Right Arithmetic Immediate, srai
- Shift Left Logical Word Immediate, slliw
- Shift Right Logical Word Immediate, srliw
- Shift Right Arithmetic Word Immediate, sraiw
Change-Id: Iad34ccd036c11630409f84f6de2b939224e100e6
Signed-off-by: Ian Jiang <[email protected]>
---
M src/arch/riscv/isa/decoder.isa
M src/arch/riscv/isa/formats/standard.isa
2 files changed, 21 insertions(+), 0 deletions(-)
diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index 8fcfba6..f9bb22a 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -413,9 +413,13 @@
0x0: addi({{
Rd_sd = Rs1_sd + imm;
}});
+ }
+ format IShiftOp {
0x1: slli({{
Rd = Rs1 << SHAMT6;
}});
+ }
+ format IOp {
0x2: slti({{
Rd = (Rs1_sd < imm) ? 1 : 0;
}});
@@ -425,6 +429,8 @@
0x4: xori({{
Rd = Rs1 ^ imm;
}}, uint64_t);
+ }
+ format IShiftOp {
0x5: decode SRTYPE {
0x0: srli({{
Rd = Rs1 >> SHAMT6;
@@ -433,6 +439,8 @@
Rd_sd = Rs1_sd >> SHAMT6;
}});
}
+ }
+ format IOp {
0x6: ori({{
Rd = Rs1 | imm;
}}, uint64_t);
@@ -451,6 +459,8 @@
0x0: addiw({{
Rd_sd = Rs1_sw + imm;
}}, int32_t);
+ }
+ format IShiftOp {
0x1: slliw({{
Rd_sd = Rs1_sw << SHAMT5;
}});
diff --git a/src/arch/riscv/isa/formats/standard.isa
b/src/arch/riscv/isa/formats/standard.isa
index 15d2681..b96cf9a 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -309,6 +309,17 @@
exec_output = ImmExecute.subst(iop)
}};
+def format IShiftOp(code, imm_type='uint64_t', *opt_flags) {{
+ regs = ['_destRegIdx[0]','_srcRegIdx[0]']
+ iop = InstObjParams(name, Name, 'ImmOp<%s>' % imm_type,
+ {'code': code, 'imm_code': 'imm = IMM12&0x03F;',
+ 'regs': ','.join(regs)}, opt_flags)
+ header_output = ImmDeclare.subst(iop)
+ decoder_output = ImmConstructor.subst(iop)
+ decode_block = BasicDecode.subst(iop)
+ exec_output = ImmExecute.subst(iop)
+}};
+
def format BOp(code, *opt_flags) {{
imm_code = """
imm = BIMM12BITS4TO1 << 1 |
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Iad34ccd036c11630409f84f6de2b939224e100e6
Gerrit-Change-Number: 22563
Gerrit-PatchSet: 1
Gerrit-Owner: Ian Jiang <[email protected]>
Gerrit-MessageType: newchange
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