Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/23104 )
Change subject: arch-arm: Reorder arch/arm/registers.hh constants
......................................................................
arch-arm: Reorder arch/arm/registers.hh constants
This is putting some order in the constants definition, respecting
the description which divides:
* Constants Related to the number of registers
(example: const int NumFloatRegs = 0)
from:
* Semantically meaningful register indices (to indicate special
registers)
(example: const int INTRLVREG0 = NumVecV8ArchRegs + NumVecSpecialRegs)
Change-Id: I1760b7f786b6f6becbe8ab445e65fc3fa17206cb
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikole...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23104
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/arch/arm/registers.hh
1 file changed, 17 insertions(+), 14 deletions(-)
Approvals:
Nikos Nikoleris: Looks good to me, approved
Giacomo Travaglini: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh
index 1c9ec26..7f6309b 100644
--- a/src/arch/arm/registers.hh
+++ b/src/arch/arm/registers.hh
@@ -79,32 +79,26 @@
using VecPredRegContainer = VecPredReg::Container;
// Constants Related to the number of registers
+// Int, Float, CC, Misc
const int NumIntArchRegs = NUM_ARCH_INTREGS;
-// The number of single precision floating point registers
+const int NumIntRegs = NUM_INTREGS;
+const int NumFloatRegs = 0; // Float values are stored in the VecRegs
+const int NumCCRegs = NUM_CCREGS;
+const int NumMiscRegs = NUM_MISCREGS;
+
+// Vec, PredVec
const int NumFloatV7ArchRegs = 64;
const int NumVecV7ArchRegs = 64;
const int NumVecV8ArchRegs = 32;
const int NumVecSpecialRegs = 8;
-
const int NumVecIntrlvRegs = 4;
-const int NumIntRegs = NUM_INTREGS;
-const int NumFloatRegs = 0; // Float values are stored in the VecRegs
const int NumVecRegs = NumVecV8ArchRegs + NumVecSpecialRegs +
NumVecIntrlvRegs;
-const int VECREG_UREG0 = 32;
const int NumVecPredRegs = 18; // P0-P15, FFR, UREG0
-const int PREDREG_FFR = 16;
-const int PREDREG_UREG0 = 17;
-const int NumCCRegs = NUM_CCREGS;
-const int NumMiscRegs = NUM_MISCREGS;
-const int INTRLVREG0 = NumVecV8ArchRegs + NumVecSpecialRegs;
-const int INTRLVREG1 = INTRLVREG0 + 1;
-const int INTRLVREG2 = INTRLVREG0 + 2;
-const int INTRLVREG3 = INTRLVREG0 + 3;
const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumVecRegs +
NumVecPredRegs + NumMiscRegs;
-// semantically meaningful register indices
+// Semantically meaningful register indices
const int ReturnValueReg = 0;
const int ReturnValueReg1 = 1;
const int ReturnValueReg2 = 2;
@@ -121,6 +115,15 @@
const int ZeroReg = INTREG_ZERO;
+// Vec, PredVec indices
+const int INTRLVREG0 = NumVecV8ArchRegs + NumVecSpecialRegs;
+const int INTRLVREG1 = INTRLVREG0 + 1;
+const int INTRLVREG2 = INTRLVREG0 + 2;
+const int INTRLVREG3 = INTRLVREG0 + 3;
+const int VECREG_UREG0 = 32;
+const int PREDREG_FFR = 16;
+const int PREDREG_UREG0 = 17;
+
const int SyscallNumReg = ReturnValueReg;
const int SyscallPseudoReturnReg = ReturnValueReg;
const int SyscallSuccessReg = ReturnValueReg;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I1760b7f786b6f6becbe8ab445e65fc3fa17206cb
Gerrit-Change-Number: 23104
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Gabe Black <gabebl...@google.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Nikos Nikoleris <nikos.nikole...@arm.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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