Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/23527 )
Change subject: arch: Add raw read/writeMem helpers
......................................................................
arch: Add raw read/writeMem helpers
With some exceptions (in arm/x86) the standard memory read/write interface
for instructions relies upon the helper functions in
src/arch/generic/memhelpers.hh
which wrap the ExecContext interface.
(readMem, writeMem...)
Those helpers rely on the source/destination data to be provided (as
expected) but not on the size of the transaction. The latter gets
evaluated via the host size of the source/destination data
(sizeof(MemT)).
For this reason some instructions, which are instead using an
incompatible MemT data (as an example, a SIMD operation loading data in
an array of integers), make direct use of the ExecContext interface,
which is simply requesting for a pointer and a number of bytes.
Some other instructions are using the ExecContext interface since the
helpers do not accept a byteEnable argument.
This patch is adding some helpers to address these issues. The idea is
to deprecate direct usage of the ExecContext APIs.
These new wrappers do not work with the type detection mechanism
to evaluate the number of bytes we are accessing.
JIRA: https://gem5.atlassian.net/browse/GEM5-196
Change-Id: I5b822d278bdf325a68a01aa1861b6487c6628245
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/arch/generic/memhelpers.hh
1 file changed, 50 insertions(+), 6 deletions(-)
diff --git a/src/arch/generic/memhelpers.hh b/src/arch/generic/memhelpers.hh
index 62866bf..234bd15 100644
--- a/src/arch/generic/memhelpers.hh
+++ b/src/arch/generic/memhelpers.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013 ARM Limited
+ * Copyright (c) 2013, 2019 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -50,6 +50,15 @@
#include "sim/byteswap.hh"
#include "sim/insttracer.hh"
+template <class XC>
+Fault
+initiateMemRead(XC *xc, Trace::InstRecord *traceData, Addr addr,
+ std::size_t size, Request::Flags flags,
+ const std::vector<bool> &byte_enable)
+{
+ return xc->initiateMemRead(addr, size, flags, byte_enable);
+}
+
/// Initiate a read from memory in timing mode. Note that the 'mem'
/// parameter is unused; only the type of that parameter is used
/// to determine the size of the access.
@@ -58,7 +67,9 @@
initiateMemRead(XC *xc, Trace::InstRecord *traceData, Addr addr,
MemT &mem, Request::Flags flags)
{
- return xc->initiateMemRead(addr, sizeof(MemT), flags);
+ const std::vector<bool> byte_enable(sizeof(MemT), true);
+ return initiateMemRead(xc, traceData, addr, sizeof(MemT),
+ flags, byte_enable);
}
/// Extract the data returned from a timing mode read.
@@ -86,13 +97,25 @@
}
/// Read from memory in atomic mode.
+template <class XC>
+Fault
+readMemAtomic(XC *xc, Trace::InstRecord *traceData, Addr addr, uint8_t
*mem,
+ std::size_t size, Request::Flags flags,
+ const std::vector<bool> &byte_enable)
+{
+ return xc->readMem(addr, mem, size, flags, byte_enable);
+}
+
+/// Read from memory in atomic mode.
template <ByteOrder Order, class XC, class MemT>
Fault
readMemAtomic(XC *xc, Trace::InstRecord *traceData, Addr addr, MemT &mem,
Request::Flags flags)
{
memset(&mem, 0, sizeof(mem));
- Fault fault = xc->readMem(addr, (uint8_t *)&mem, sizeof(MemT), flags);
+ const std::vector<bool> byte_enable(sizeof(MemT), true);
+ Fault fault = readMemAtomic(xc, traceData, addr, (uint8_t*)&mem,
+ sizeof(MemT), flags, byte_enable);
if (fault == NoFault) {
mem = gtoh(mem, Order);
if (traceData)
@@ -119,6 +142,15 @@
}
/// Write to memory in timing mode.
+template <class XC>
+Fault
+writeMemTiming(XC *xc, Trace::InstRecord *traceData, uint8_t *mem, Addr
addr,
+ std::size_t size, Request::Flags flags, uint64_t *res,
+ const std::vector<bool> &byte_enable)
+{
+ return xc->writeMem(mem, size, addr, flags, res, byte_enable);
+}
+
template <ByteOrder Order, class XC, class MemT>
Fault
writeMemTiming(XC *xc, Trace::InstRecord *traceData, MemT mem, Addr addr,
@@ -128,7 +160,9 @@
traceData->setData(mem);
}
mem = htog(mem, Order);
- return xc->writeMem((uint8_t *)&mem, sizeof(MemT), addr, flags, res);
+ const std::vector<bool> byte_enable(sizeof(MemT), true);
+ return writeMemTiming(xc, traceData, (uint8_t*)&mem, addr,
+ sizeof(MemT), flags, res, byte_enable);
}
template <class XC, class MemT>
@@ -150,6 +184,15 @@
}
/// Write to memory in atomic mode.
+template <class XC>
+Fault
+writeMemAtomic(XC *xc, Trace::InstRecord *traceData, uint8_t *mem,
+ Addr addr, std::size_t size, Request::Flags flags,
+ uint64_t *res, const std::vector<bool> &byte_enable)
+{
+ return xc->writeMem(mem, size, addr, flags, res, byte_enable);
+}
+
template <ByteOrder Order, class XC, class MemT>
Fault
writeMemAtomic(XC *xc, Trace::InstRecord *traceData, const MemT &mem,
@@ -159,8 +202,9 @@
traceData->setData(mem);
}
MemT host_mem = htog(mem, Order);
- Fault fault =
- xc->writeMem((uint8_t *)&host_mem, sizeof(MemT), addr, flags,
res);
+ const std::vector<bool> byte_enable(sizeof(MemT), true);
+ Fault fault = writeMemAtomic(xc, traceData, (uint8_t*)&host_mem,
+ addr, sizeof(MemT), flags, res,
byte_enable);
if (fault == NoFault && res != NULL) {
if (flags & Request::MEM_SWAP || flags & Request::MEM_SWAP_COND)
*(MemT *)res = gtoh(*(MemT *)res, Order);
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I5b822d278bdf325a68a01aa1861b6487c6628245
Gerrit-Change-Number: 23527
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: newchange
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