Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/23529 )
Change subject: arch-x86: Add byteEnable mask in x86 memhelpers
......................................................................
arch-x86: Add byteEnable mask in x86 memhelpers
Next patch will make the byteEnable mandatory in the ExecContext
interface so we need to amend the existing helpers to make them
use generate the boolean vector.
JIRA: https://gem5.atlassian.net/browse/GEM5-196
Change-Id: Ib24550aa1e22049487ef4ec2748b786be456d342
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/arch/x86/memhelpers.hh
1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/src/arch/x86/memhelpers.hh b/src/arch/x86/memhelpers.hh
index 424b729..af09bb5 100644
--- a/src/arch/x86/memhelpers.hh
+++ b/src/arch/x86/memhelpers.hh
@@ -47,7 +47,8 @@
initiateMemRead(ExecContext *xc, Trace::InstRecord *traceData, Addr addr,
unsigned dataSize, Request::Flags flags)
{
- return xc->initiateMemRead(addr, dataSize, flags);
+ const std::vector<bool> byte_enable(dataSize, true);
+ return xc->initiateMemRead(addr, dataSize, flags, byte_enable);
}
static void
@@ -108,7 +109,9 @@
uint64_t &mem, unsigned dataSize, Request::Flags flags)
{
memset(&mem, 0, sizeof(mem));
- Fault fault = xc->readMem(addr, (uint8_t *)&mem, dataSize, flags);
+ const std::vector<bool> byte_enable(dataSize, true);
+ Fault fault = xc->readMem(addr, (uint8_t *)&mem, dataSize,
+ flags, byte_enable);
if (fault == NoFault) {
// If LE to LE, this is a nop, if LE to BE, the actual data ends up
// in the right place because the LSBs where at the low addresses
on
@@ -126,8 +129,10 @@
unsigned flags)
{
std::array<T, N> real_mem;
+ const auto size = sizeof(T) * N;
+ const std::vector<bool> byte_enable(size, true);
Fault fault = xc->readMem(addr, (uint8_t *)&real_mem,
- sizeof(T) * N, flags);
+ size, flags, byte_enable);
if (fault == NoFault) {
real_mem = letoh(real_mem);
for (int i = 0; i < N; i++)
@@ -168,8 +173,10 @@
for (int i = 0; i < N; i++)
real_mem[i] = mem[i];
real_mem = htole(real_mem);
- return xc->writeMem((uint8_t *)&real_mem, sizeof(T) * N,
- addr, flags, res);
+ const auto size = sizeof(T) * N;
+ const std::vector<bool> byte_enable(size, true);
+ return xc->writeMem((uint8_t *)&real_mem, size,
+ addr, flags, res, byte_enable);
}
static Fault
@@ -180,7 +187,9 @@
if (traceData)
traceData->setData(mem);
mem = htole(mem);
- return xc->writeMem((uint8_t *)&mem, dataSize, addr, flags, res);
+ const std::vector<bool> byte_enable(dataSize, true);
+ return xc->writeMem((uint8_t *)&mem, dataSize, addr, flags,
+ res, byte_enable);
}
template <size_t N>
@@ -210,8 +219,9 @@
if (traceData)
traceData->setData(mem);
uint64_t host_mem = htole(mem);
- Fault fault =
- xc->writeMem((uint8_t *)&host_mem, dataSize, addr, flags, res);
+ const std::vector<bool> byte_enable(dataSize, true);
+ Fault fault = xc->writeMem((uint8_t *)&host_mem, dataSize, addr,
+ flags, res, byte_enable);
if (fault == NoFault && res)
*res = letoh(*res);
return fault;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/23529
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ib24550aa1e22049487ef4ec2748b786be456d342
Gerrit-Change-Number: 23529
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: newchange
_______________________________________________
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev