Gabe, thanks for raising this up. I had tested this when I made that patch, and I retested it now and it seems fine, let us know if you find any problems with it.
I've just tested manually with a tiny userland freestanding executable on SE: .global _start _start: fmov d0, 1.5 fmov d1, 2.5 fadd d2, d0, d1 fmov d3, 4.0 fcmp d2, d3 You can compile and run it with: aarch64-linux-gnu-as -ggdb3 -o main.o main.S aarch64-linux-gnu-ld -o main.out main.o and then from GDB step with si and print registers with: i r d0 d1 d2 d3 I considered automating this with pexpect, but it is a bit complicated/flimsy, so I don't think it is worth adding this type of automated test for now, which is likely to break more often than the feature itself. ________________________________ From: Gabe Black <[email protected]> Sent: Thursday, December 5, 2019 5:36 AM To: gem5 Developer List <[email protected]> Cc: Ciro Santilli <[email protected]>; Giacomo Travaglini <[email protected]> Subject: Ordering of regs in the ARM GDB stub Hi Ciro and Giacomo. I noticed in this CL: https://gem5-review.googlesource.com/c/14498 The GDB stub was updated from using floating point registers to vector registers, something I'm doing to fix ARMv8 KVM CPU at the moment. I noticed that before the registers were, for example, read as: i + 2 => i + 0 i + 3 => i + 1 i + 0 => i + 2 i + 1 => i + 4 Where as after the change the mapping appears to be more like to like. It's not 100% clear if that's just an artifact of how things were stored, or if this is an actual (and/or intentional) change in behavior, but I wanted to mention it since I'm not sure how often the GDB stub functionality is tested. Gabe _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
