Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/24648 )
Change subject: cpu: Remove alpha specialized code.
......................................................................
cpu: Remove alpha specialized code.
Change-Id: I770132af2f11ed232a100ab8bef942f17789ef36
---
M src/cpu/BaseCPU.py
M src/cpu/checker/cpu_impl.hh
M src/cpu/minor/exec_context.hh
M src/cpu/minor/fetch1.cc
M src/cpu/o3/commit_impl.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/fetch.hh
M src/cpu/reg_class.hh
M src/cpu/simple/base.cc
9 files changed, 8 insertions(+), 44 deletions(-)
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 57f0f2f..a7d37bf 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -62,12 +62,7 @@
default_tracer = ExeTracer()
-if buildEnv['TARGET_ISA'] == 'alpha':
- from m5.objects.AlphaTLB import AlphaDTB as ArchDTB, AlphaITB as
ArchITB
- from m5.objects.AlphaInterrupts import AlphaInterrupts as
ArchInterrupts
- from m5.objects.AlphaISA import AlphaISA as ArchISA
- ArchISAsParam = VectorParam.AlphaISA
-elif buildEnv['TARGET_ISA'] == 'sparc':
+if buildEnv['TARGET_ISA'] == 'sparc':
from m5.objects.SparcTLB import SparcTLB as ArchDTB, SparcTLB as
ArchITB
from m5.objects.SparcInterrupts import SparcInterrupts as
ArchInterrupts
from m5.objects.SparcISA import SparcISA as ArchISA
diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index fce4a9f..f4b43b2 100644
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -207,9 +207,6 @@
// maintain $r0 semantics
thread->setIntReg(ZeroReg, 0);
-#if THE_ISA == ALPHA_ISA
- thread->setFloatReg(ZeroReg, 0);
-#endif
// Check if any recent PC changes match up with anything we
// expect to happen. This is mostly to check if traps or
diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh
index 4cc41c6..2b1b530 100644
--- a/src/cpu/minor/exec_context.hh
+++ b/src/cpu/minor/exec_context.hh
@@ -99,9 +99,6 @@
setPredicate(inst->readPredicate());
setMemAccPredicate(inst->readMemAccPredicate());
thread.setIntReg(TheISA::ZeroReg, 0);
-#if THE_ISA == ALPHA_ISA
- thread.setFloatReg(TheISA::ZeroReg, 0);
-#endif
}
~ExecContext()
diff --git a/src/cpu/minor/fetch1.cc b/src/cpu/minor/fetch1.cc
index 465372a..d302f0f 100644
--- a/src/cpu/minor/fetch1.cc
+++ b/src/cpu/minor/fetch1.cc
@@ -196,15 +196,7 @@
/* Step the PC for the next line onto the line aligned next address.
* Note that as instructions can span lines, this PC is only a
* reliable 'new' PC if the next line has a new stream sequence
number. */
-#if THE_ISA == ALPHA_ISA
- /* Restore the low bits of the PC used as address space flags */
- Addr pc_low_bits = thread.pc.instAddr() &
- ((Addr) (1 << sizeof(TheISA::MachInst)) - 1);
-
- thread.pc.set(aligned_pc + request_size + pc_low_bits);
-#else
thread.pc.set(aligned_pc + request_size);
-#endif
}
std::ostream &
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index fa2d724..fc92707 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -1053,11 +1053,8 @@
// Set the doneSeqNum to the youngest committed
instruction.
toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
- if (tid == 0) {
- canHandleInterrupts = (!head_inst->isDelayedCommit())
&&
- ((THE_ISA != ALPHA_ISA) ||
- (!(pc[0].instAddr() & 0x3)));
- }
+ if (tid == 0)
+ canHandleInterrupts = !head_inst->isDelayedCommit();
// at this point store conditionals should either have
// been completed or predicated false
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 996f636..9276ab2 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -68,12 +68,6 @@
#include "sim/stat_control.hh"
#include "sim/system.hh"
-#if THE_ISA == ALPHA_ISA
-#include "arch/alpha/osfpal.hh"
-#include "debug/Activity.hh"
-
-#endif
-
struct BaseCPUParams;
using namespace TheISA;
@@ -227,14 +221,11 @@
// use an invalid FP register index to avoid special treatment
// of any valid FP reg.
RegIndex invalidFPReg = TheISA::NumFloatRegs + 1;
- RegIndex fpZeroReg =
- (THE_ISA == ALPHA_ISA) ? TheISA::ZeroReg : invalidFPReg;
- commitRenameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg,
- &freeList,
- vecMode);
+ commitRenameMap[tid].init(®File, TheISA::ZeroReg, invalidFPReg,
+ &freeList, vecMode);
- renameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg,
+ renameMap[tid].init(®File, TheISA::ZeroReg, invalidFPReg,
&freeList, vecMode);
}
diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index b8766ad..890e8f3 100644
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -325,7 +325,7 @@
bool
checkInterrupt(Addr pc)
{
- return (interruptPending && (THE_ISA != ALPHA_ISA || !(pc & 0x3)));
+ return interruptPending;
}
/** Squashes a specific thread and resets the PC. */
diff --git a/src/cpu/reg_class.hh b/src/cpu/reg_class.hh
index e71e938..5158137 100644
--- a/src/cpu/reg_class.hh
+++ b/src/cpu/reg_class.hh
@@ -140,9 +140,7 @@
inline bool isZeroReg() const
{
- return ((regClass == IntRegClass && regIdx == TheISA::ZeroReg) ||
- (THE_ISA == ALPHA_ISA && regClass == FloatRegClass &&
- regIdx == TheISA::ZeroReg));
+ return regClass == IntRegClass && regIdx == TheISA::ZeroReg;
}
/** @return true if it is an integer physical register. */
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 566533c..6082d89 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -491,9 +491,6 @@
// maintain $r0 semantics
thread->setIntReg(ZeroReg, 0);
-#if THE_ISA == ALPHA_ISA
- thread->setFloatReg(ZeroReg, 0);
-#endif // ALPHA_ISA
// resets predicates
t_info.setPredicate(true);
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I770132af2f11ed232a100ab8bef942f17789ef36
Gerrit-Change-Number: 24648
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabebl...@google.com>
Gerrit-MessageType: newchange
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