On 1/29/20 3:26 AM, Gabe Black wrote:
> It looks to me like this is because the MicroUopSetPCCPSR microop
> (uopSet_uop, the one actually setting the CPSR) is not marked as
> IsSerializeAfter. The macroop it's a part of is, but the flags on macroops,
> other than the one that says it's a macroop, don't matter since they are
> never executed. Their job is just to spit out microops which are executed.
> 
> The offending microop is not set as IsSerializeAfter, so the instructions
> behind it start getting processed before it's completed and updated the
> CPSR and exception level. The stack pointer index is resolved to a
> particular stack pointer at that point and reflects the old CPSR/exception
> level and not the new one.
> 
> A full fix from ARM would probably involve taking away the unused and
> slightly confusing flags from the macroop that don't do anything which I
> don't want to dig into myself. To get things working for you, you can
> *probably* just add IsSerializeAfter to MicroOupSetPCCPSR in
> arch/arm/isa/insts/macromem.isa on about line 690, right after IsMicroop.
> 
> So ['IsMicrop'] would become ['IsMicroop', 'IsSerializeAfter'].
> 
> That instruction/microop should unconditionally be IsSerializeAfter since
> it modifies state which is used to interpret register indices in later
> instructions, and if it isn't those instructions will be set up incorrectly
> like you're seeing here.

That fixed it indeed. Thank you very much! :)

Best regards,
Nils
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