Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/25013 )
Change subject: arch-arm: make MicroUopSetPCCPSR SerializeAfter
......................................................................
arch-arm: make MicroUopSetPCCPSR SerializeAfter
Updating CPSR needs to be SerializeAfter to ensure that all following
instructions are executed with the new CPSR. Otherwise, for example,
the following instructions will access the banked registers from the
previous mode.
The missing IsSerializeAfter had the consequence that the instruction
rfe (return from exception) did not work correctly with the DerivO3CPU
model.
Jira Issue: https://gem5.atlassian.net/browse/GEM5-303
Change-Id: I999623c0fc92cfcd4c3550b9cb34e8564a92e3e6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24943
Reviewed-by: Gabe Black <gabebl...@google.com>
Maintainer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Tested-by: kokoro <noreply+kok...@google.com>
(cherry picked from commit 0d665d4f9893320db4f3b5f7014a6e10c3420b69)
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25013
Reviewed-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/arch/arm/isa/insts/macromem.isa
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/isa/insts/macromem.isa
b/src/arch/arm/isa/insts/macromem.isa
index 251e5c2..d9eea19 100644
--- a/src/arch/arm/isa/insts/macromem.isa
+++ b/src/arch/arm/isa/insts/macromem.isa
@@ -691,7 +691,7 @@
'MicroSetPCCPSR',
{'code': setPCCPSRDecl,
'predicate_test': predicateTest},
- ['IsMicroop'])
+ ['IsMicroop', 'IsSerializeAfter'])
header_output = MicroIntImmDeclare.subst(microAddiUopIop) + \
MicroIntImmDeclare.subst(microAddXiUopIop) + \
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/25013
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I999623c0fc92cfcd4c3550b9cb34e8564a92e3e6
Gerrit-Change-Number: 25013
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Gabe Black <gabebl...@google.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Nils Asmussen <nilsasmuss...@gmail.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
_______________________________________________
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
