Hi Dan,
This is for an advanced feature :). This is used for the resource stalls
feature. Resource stalls are used to model bandwidth to different
structures. This is saying that on the transition from I to I_M0 will
access the L1D0TagArrayRead and L2TagArrayRead. In the background, this
calls checkResourceAvailable (or something like that) and if the resource
isn't available, the transition will not be allowed to proceed.
Additionally, all of the accesses are counted so you can use these counts
for things like energy models.
Let me know if you have any other questions.
Cheers,
Jason
On Tue, Feb 11, 2020 at 11:29 AM Daniel Gerzhoy <daniel.gerz...@gmail.com>
wrote:
> Hello,
>
> I went through the learning gem5 book to learn slicc (finally) and it made
> sense to me through that. But I've been looking through the
> MOESI_AMD_Base-CorePair.sm file (among others) and I've seen a syntax I
> don't understand.
>
> transition(I, C0_Store_L1miss, I_M0) {L1D0TagArrayRead, L2TagArrayRead} {
>
> So I know in the parens of "transition" are (begin_state, event, end_state)
> and that any one of those can be bracketed to do a cross product. I do not
> however understand the extra brackets after the parens with
> {L1D0TagArrayRead, L2TagArrayRead}.
>
> Any help would be greatly appreciated!
>
> Cheers,
>
> Dan Gerzhoy
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