Hello Tony Gutierrez, Onur Kayıran,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/28134
to review the following change.
Change subject: configs: Specify cache, dir, and mem cntrl interleaving
......................................................................
configs: Specify cache, dir, and mem cntrl interleaving
This changeset allows setting a variable for interleaving.
That value is used together with the number of directories to
calculate numa_high_bit, which is in turn used to set up
cache, directory, and memory controller interleaving.
A similar approach is used to set xor_low_bit, and calculate
xor_high_bit for address hashing.
Change-Id: Ia342c77c59ca2e3438db218b5c399c3373618320
---
M configs/common/MemConfig.py
M configs/ruby/Ruby.py
2 files changed, 24 insertions(+), 6 deletions(-)
diff --git a/configs/common/MemConfig.py b/configs/common/MemConfig.py
index 9443520..3461a9e 100644
--- a/configs/common/MemConfig.py
+++ b/configs/common/MemConfig.py
@@ -40,7 +40,8 @@
from common import ObjectList
from common import HMC
-def create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits, intlv_size):
+def create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits, intlv_size,\
+ xor_low_bit):
"""
Helper function for creating a single memoy controller from the given
options. This function is invoked multiple times in config_mem
function
@@ -55,7 +56,10 @@
# the details of the caches here, make an educated guess. 4 MByte
# 4-way associative with 64 byte cache lines is 6 offset bits and
# 14 index bits.
- xor_low_bit = 20
+ if (xor_low_bit):
+ xor_high_bit = xor_low_bit + intlv_bits - 1
+ else:
+ xor_high_bit = 0
# Create an instance so we can figure out the address
# mapping and row-buffer size
@@ -81,8 +85,7 @@
ctrl.range = m5.objects.AddrRange(r.start, size = r.size(),
intlvHighBit = \
intlv_low_bit + intlv_bits - 1,
- xorHighBit = \
- xor_low_bit + intlv_bits - 1,
+ xorHighBit = xor_high_bit,
intlvBits = intlv_bits,
intlvMatch = i)
return ctrl
diff --git a/configs/ruby/Ruby.py b/configs/ruby/Ruby.py
index e69784f..9bceaa3 100644
--- a/configs/ruby/Ruby.py
+++ b/configs/ruby/Ruby.py
@@ -76,6 +76,15 @@
parser.add_option("--numa-high-bit", type="int", default=0,
help="high order address bit to use for numa
mapping. " \
"0 = highest bit, not specified = lowest bit")
+ parser.add_option("--interleaving-bits", type="int", default=0,
+ help="number of bits to specify interleaving " \
+ "in directory, memory controllers and caches. "
+ "0 = not specified")
+ parser.add_option("--xor-low-bit", type="int", default=20,
+ help="hashing bit for channel selection" \
+ "see MemConfig for explanation of the default"\
+ "parameter. If set to 0, xor_high_bit is also"\
+ "set to 0.")
parser.add_option("--recycle-latency", type="int", default=10,
help="Recycle latency for ruby controller input
buffers")
@@ -86,7 +95,13 @@
Network.define_options(parser)
def setup_memory_controllers(system, ruby, dir_cntrls, options):
- ruby.block_size_bytes = options.cacheline_size
+ if (options.numa_high_bit):
+ block_size_bits = options.numa_high_bit + 1 - \
+ int(math.log(options.num_dirs, 2))
+ ruby.block_size_bytes = 2 ** (block_size_bits)
+ else:
+ ruby.block_size_bytes = options.cacheline_size
+
ruby.memory_size_bits = 48
index = 0
@@ -117,7 +132,7 @@
mem_type = ObjectList.mem_list.get(options.mem_type)
mem_ctrl = MemConfig.create_mem_ctrl(mem_type, r, index,
options.num_dirs, int(math.log(options.num_dirs, 2)),
- intlv_size)
+ intlv_size, options.xor_low_bit)
if options.access_backing_store:
mem_ctrl.kvm_map=False
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia342c77c59ca2e3438db218b5c399c3373618320
Gerrit-Change-Number: 28134
Gerrit-PatchSet: 1
Gerrit-Owner: Anthony Gutierrez <anthony.gutier...@amd.com>
Gerrit-Reviewer: Onur Kayıran <onur.kayi...@amd.com>
Gerrit-Reviewer: Tony Gutierrez <anthony.gutier...@amd.com>
Gerrit-MessageType: newchange
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