Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/21921 )
Change subject: mem-ruby: Check on PerfectCacheMemory deallocate
......................................................................
mem-ruby: Check on PerfectCacheMemory deallocate
Allowing deallocate to be called for non-existing blocks may hide
potential bugs.
Change-Id: Ida77e2db1da59d7cdb21d58968e1f17e75eaa6e0
Signed-off-by: Tiago Mück <tiago.m...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21921
Reviewed-by: Pouya Fotouhi <pfoto...@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power...@gmail.com>
Maintainer: Jason Lowe-Power <power...@gmail.com>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/mem/ruby/structures/PerfectCacheMemory.hh
1 file changed, 14 insertions(+), 1 deletion(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Pouya Fotouhi: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/structures/PerfectCacheMemory.hh
b/src/mem/ruby/structures/PerfectCacheMemory.hh
index 363e3e8..9898995 100644
--- a/src/mem/ruby/structures/PerfectCacheMemory.hh
+++ b/src/mem/ruby/structures/PerfectCacheMemory.hh
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2019 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
* All rights reserved.
*
@@ -138,7 +150,8 @@
inline void
PerfectCacheMemory<ENTRY>::deallocate(Addr address)
{
- m_map.erase(makeLineAddress(address));
+ auto num_erased M5_VAR_USED = m_map.erase(makeLineAddress(address));
+ assert(num_erased == 1);
}
// Returns with the physical address of the conflicting cache line
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ida77e2db1da59d7cdb21d58968e1f17e75eaa6e0
Gerrit-Change-Number: 21921
Gerrit-PatchSet: 4
Gerrit-Owner: Tiago Mück <tiago.m...@arm.com>
Gerrit-Reviewer: Daniel Carvalho <oda...@yahoo.com.br>
Gerrit-Reviewer: Jason Lowe-Power <power...@gmail.com>
Gerrit-Reviewer: John Alsop <johnathan.al...@amd.com>
Gerrit-Reviewer: Matthew Poremba <matthew.pore...@amd.com>
Gerrit-Reviewer: Pouya Fotouhi <pfoto...@ucdavis.edu>
Gerrit-Reviewer: Tiago Mück <tiago.m...@arm.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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