Ayaz Akram has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28667 )
Change subject: mem-ruby: Deep renaming of Prefetcher to RubyPrefetcher
......................................................................
mem-ruby: Deep renaming of Prefetcher to RubyPrefetcher
A recent change (https://gem5-review.googlesource.com/c/
public/gem5/+/27949) updated the ruby prefetcher name,
which breaks the use of old name in some SLICC files.
This change makes sure that the new name is used at all
places.
Issue-On: https://gem5.atlassian.net/browse/GEM5-498
Change-Id: Ic667b61eac13dc7c267cee7dce3aa970f7ae9a8b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28667
Reviewed-by: Timothy Hayes <timothy.ha...@arm.com>
Maintainer: Jason Lowe-Power <power...@gmail.com>
Tested-by: kokoro <noreply+kok...@google.com>
---
M configs/ruby/MESI_Three_Level.py
M configs/ruby/MESI_Two_Level.py
M src/mem/ruby/SConscript
M src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
M src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
M src/mem/ruby/protocol/RubySlicc_Types.sm
R src/mem/ruby/structures/RubyPrefetcher.cc
R src/mem/ruby/structures/RubyPrefetcher.hh
M src/mem/ruby/structures/RubyPrefetcher.py
M src/mem/ruby/structures/SConscript
M src/mem/slicc/symbols/StateMachine.py
11 files changed, 19 insertions(+), 15 deletions(-)
Approvals:
Timothy Hayes: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/configs/ruby/MESI_Three_Level.py
b/configs/ruby/MESI_Three_Level.py
index 61d6c52..0bd893e 100644
--- a/configs/ruby/MESI_Three_Level.py
+++ b/configs/ruby/MESI_Three_Level.py
@@ -121,7 +121,7 @@
clk_domain = system.cpu[i].clk_domain
# Ruby prefetcher
- prefetcher = RubyPrefetcher.Prefetcher(
+ prefetcher = RubyPrefetcher(
num_streams=16,
unit_filter = 256,
nonunit_filter = 256,
diff --git a/configs/ruby/MESI_Two_Level.py b/configs/ruby/MESI_Two_Level.py
index 8d2e01f..3ddf8ef 100644
--- a/configs/ruby/MESI_Two_Level.py
+++ b/configs/ruby/MESI_Two_Level.py
@@ -78,7 +78,7 @@
start_index_bit = block_size_bits,
is_icache = False)
- prefetcher = RubyPrefetcher.Prefetcher()
+ prefetcher = RubyPrefetcher()
# the ruby random tester reuses num_cpus to specify the
# number of cpu ports connected to the tester object, which
diff --git a/src/mem/ruby/SConscript b/src/mem/ruby/SConscript
index 8c22ae4..fc90f8a 100644
--- a/src/mem/ruby/SConscript
+++ b/src/mem/ruby/SConscript
@@ -126,7 +126,7 @@
MakeInclude('structures/DirectoryMemory.hh')
MakeInclude('structures/PerfectCacheMemory.hh')
MakeInclude('structures/PersistentTable.hh')
-MakeInclude('structures/Prefetcher.hh')
+MakeInclude('structures/RubyPrefetcher.hh')
MakeInclude('structures/TBETable.hh')
MakeInclude('structures/TimerTable.hh')
MakeInclude('structures/WireBuffer.hh')
diff --git a/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
b/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
index 3639ef2..4de4a29 100644
--- a/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
+++ b/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
@@ -46,7 +46,7 @@
Cycles response_latency := 2;
bool send_evictions;
- Prefetcher * prefetcher;
+ RubyPrefetcher * prefetcher;
bool enable_prefetch := "False";
// From this node's L0 cache to the network
diff --git a/src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
b/src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
index 7c83478..3e3580f 100644
--- a/src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
+++ b/src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
@@ -30,7 +30,7 @@
: Sequencer * sequencer;
CacheMemory * L1Icache;
CacheMemory * L1Dcache;
- Prefetcher * prefetcher;
+ RubyPrefetcher * prefetcher;
int l2_select_num_bits;
Cycles l1_request_latency := 2;
Cycles l1_response_latency := 2;
diff --git a/src/mem/ruby/protocol/RubySlicc_Types.sm
b/src/mem/ruby/protocol/RubySlicc_Types.sm
index 66d84fc..6ab0f3f 100644
--- a/src/mem/ruby/protocol/RubySlicc_Types.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Types.sm
@@ -246,7 +246,7 @@
bool isSet(Addr);
}
-structure (Prefetcher, external = "yes") {
+structure (RubyPrefetcher, external = "yes") {
void observeMiss(Addr, RubyRequestType);
void observePfHit(Addr);
void observePfMiss(Addr);
diff --git a/src/mem/ruby/structures/Prefetcher.cc
b/src/mem/ruby/structures/RubyPrefetcher.cc
similarity index 99%
rename from src/mem/ruby/structures/Prefetcher.cc
rename to src/mem/ruby/structures/RubyPrefetcher.cc
index 0602115..8646b99 100644
--- a/src/mem/ruby/structures/Prefetcher.cc
+++ b/src/mem/ruby/structures/RubyPrefetcher.cc
@@ -38,7 +38,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#include "mem/ruby/structures/Prefetcher.hh"
+#include "mem/ruby/structures/RubyPrefetcher.hh"
#include "base/bitfield.hh"
#include "debug/RubyPrefetcher.hh"
@@ -46,7 +46,7 @@
#include "mem/ruby/system/RubySystem.hh"
RubyPrefetcher*
-PrefetcherParams::create()
+RubyPrefetcherParams::create()
{
return new RubyPrefetcher(this);
}
diff --git a/src/mem/ruby/structures/Prefetcher.hh
b/src/mem/ruby/structures/RubyPrefetcher.hh
similarity index 98%
rename from src/mem/ruby/structures/Prefetcher.hh
rename to src/mem/ruby/structures/RubyPrefetcher.hh
index 4d2513f..b691d3d 100644
--- a/src/mem/ruby/structures/Prefetcher.hh
+++ b/src/mem/ruby/structures/RubyPrefetcher.hh
@@ -51,7 +51,7 @@
#include "mem/ruby/slicc_interface/AbstractController.hh"
#include "mem/ruby/slicc_interface/RubyRequest.hh"
#include "mem/ruby/system/RubySystem.hh"
-#include "params/Prefetcher.hh"
+#include "params/RubyPrefetcher.hh"
#include "sim/sim_object.hh"
#include "sim/system.hh"
@@ -93,7 +93,7 @@
class RubyPrefetcher : public SimObject
{
public:
- typedef PrefetcherParams Params;
+ typedef RubyPrefetcherParams Params;
RubyPrefetcher(const Params *p);
~RubyPrefetcher();
diff --git a/src/mem/ruby/structures/RubyPrefetcher.py
b/src/mem/ruby/structures/RubyPrefetcher.py
index d762ba5..38397c3 100644
--- a/src/mem/ruby/structures/RubyPrefetcher.py
+++ b/src/mem/ruby/structures/RubyPrefetcher.py
@@ -42,10 +42,10 @@
from m5.objects.System import System
-class Prefetcher(SimObject):
- type = 'Prefetcher'
+class RubyPrefetcher(SimObject):
+ type = 'RubyPrefetcher'
cxx_class = 'RubyPrefetcher'
- cxx_header = "mem/ruby/structures/Prefetcher.hh"
+ cxx_header = "mem/ruby/structures/RubyPrefetcher.hh"
num_streams = Param.UInt32(4,
"Number of prefetch streams to be allocated")
@@ -58,3 +58,7 @@
cross_page = Param.Bool(False, """True if prefetched address can be on
a
page different from the observed address""")
sys = Param.System(Parent.any, "System this prefetcher belongs to")
+
+class Prefetcher(RubyPrefetcher):
+ """DEPRECATED"""
+ pass
diff --git a/src/mem/ruby/structures/SConscript
b/src/mem/ruby/structures/SConscript
index 9e2bde9..0cf0559 100644
--- a/src/mem/ruby/structures/SConscript
+++ b/src/mem/ruby/structures/SConscript
@@ -40,6 +40,6 @@
Source('CacheMemory.cc')
Source('WireBuffer.cc')
Source('PersistentTable.cc')
-Source('Prefetcher.cc')
+Source('RubyPrefetcher.cc')
Source('TimerTable.cc')
Source('BankedArray.cc')
diff --git a/src/mem/slicc/symbols/StateMachine.py
b/src/mem/slicc/symbols/StateMachine.py
index 0904ac6..1263344 100644
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -61,7 +61,7 @@
"MemoryControl": "MemoryControl",
"MessageBuffer": "MessageBuffer",
"DMASequencer": "DMASequencer",
- "Prefetcher":"Prefetcher",
+ "RubyPrefetcher":"RubyPrefetcher",
"Cycles":"Cycles",
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: release-staging-v20.0.0.0
Gerrit-Change-Id: Ic667b61eac13dc7c267cee7dce3aa970f7ae9a8b
Gerrit-Change-Number: 28667
Gerrit-PatchSet: 4
Gerrit-Owner: Ayaz Akram <yazak...@ucdavis.edu>
Gerrit-Reviewer: Ayaz Akram <yazak...@ucdavis.edu>
Gerrit-Reviewer: Gabe Black <gabebl...@google.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Jason Lowe-Power <power...@gmail.com>
Gerrit-Reviewer: Pouya Fotouhi <pfoto...@ucdavis.edu>
Gerrit-Reviewer: Timothy Hayes <timothy.ha...@arm.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-CC: Bobby R. Bruce <bbr...@ucdavis.edu>
Gerrit-MessageType: merged
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