Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28768 )
Change subject: arch-arm: CPTR.FPEN controlling SVE enablement
......................................................................
arch-arm: CPTR.FPEN controlling SVE enablement
CheckSveEnabled shouldn't check for .ZEN only.
SVE instructions require Advanced SIMD to be supported as
well (CPTR.FPEN) with the caveat of ZEN check having priority
over the FPEN.
Change-Id: Ia1b5f7df3e25e7ffcad472542cb973635f62637b
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Reviewed-by: Ciro Santilli <ciro.santi...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28768
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/arch/arm/insts/static_inst.cc
1 file changed, 17 insertions(+), 4 deletions(-)
Approvals:
Ciro Santilli: Looks good to me, approved
Giacomo Travaglini: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/insts/static_inst.cc
b/src/arch/arm/insts/static_inst.cc
index 6da8b77..9ece0e6 100644
--- a/src/arch/arm/insts/static_inst.cc
+++ b/src/arch/arm/insts/static_inst.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2014, 2016-2019 ARM Limited
+ * Copyright (c) 2010-2014, 2016-2020 ARM Limited
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
@@ -987,20 +987,33 @@
ArmStaticInst::checkSveEnabled(ThreadContext *tc, CPSR cpsr, CPACR cpacr)
const
{
const ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
- if ((el == EL0 && cpacr.zen != 0x3) ||
- (el == EL1 && !(cpacr.zen & 0x1)))
- return sveAccessTrap(EL1);
+ // Check if access disabled in CPACR_EL1
+ if (el <= EL1 && !ELIsInHost(tc, el)) {
+ if ((el == EL0 && cpacr.zen == 0x1) ||
+ (!(cpacr.zen & 0x1)))
+ return sveAccessTrap(EL1);
+ if ((el == EL0 && cpacr.fpen == 0x1) ||
+ (!(cpacr.fpen & 0x1)))
+ return advSIMDFPAccessTrap64(EL1);
+ }
+
+ // Check if access disabled in CPTR_EL2
if (ArmSystem::haveVirtualization(tc) && el <= EL2) {
CPTR cptr_en_check = tc->readMiscReg(MISCREG_CPTR_EL2);
if (cptr_en_check.tz)
return sveAccessTrap(EL2);
+ if (cptr_en_check.tfp)
+ return advSIMDFPAccessTrap64(EL2);
}
+ // Check if access disabled in CPTR_EL3
if (ArmSystem::haveSecurity(tc)) {
CPTR cptr_en_check = tc->readMiscReg(MISCREG_CPTR_EL3);
if (!cptr_en_check.ez)
return sveAccessTrap(EL3);
+ if (cptr_en_check.tfp)
+ return advSIMDFPAccessTrap64(EL3);
}
return NoFault;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia1b5f7df3e25e7ffcad472542cb973635f62637b
Gerrit-Change-Number: 28768
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Ciro Santilli <ciro.santi...@arm.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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