Hello,

This is my first time posting here, so apologies if I made any mistakes.

The last time I checked the develop branch, gem5 has not yet supported the
AVX512. And searching the mail list I do not see any plan for that. Is
there any ongoing development to support that? If not, I am happy to
contribute my code. During my research, I have developed partial support
for AVX512 (and AVX-256 as a by-product), which I hope would be useful for
others.

My implementation so far is a straightforward extension to the existing SSE
instructions. To summarize it:

- Like SSE implementation, the 512-bit register is broken into 8 64-bit
sub-register. This may not be a good design. Any suggestions are welcome.
- Unlike SSE implementation, most of the instructions are broken into a
single microop. For example, a 512-bit 'vaddps' is decoded into one 'vaddf'
microop instead of eight.
- Currently, it supports common arithmetic instructions (add, mul, etc.)
and basic data movement (load, store, mov, extract, insert, etc.).
- No support for masking.

If you guys are interested, I am willing to clean my code and submit for
review. I may need some guidance on:

- Design of the vector register file. My implementation directly follows
the SSE instructions to minimize the work. Is there any better way to do
this?
- If I am going to merge my code, what is a good submission plan? I am
thinking about first committing the skeleton code with a simple 'vaddps'
instruction, and then for other instructions.
- Testing: This is probably the most important one. Currently, I manually
test my code by simulating small programs. What is the best way to write
tests for new instructions? Should I try unit testing for binary testing?

Thank you for reading this long post. Any feedback is welcome.

*王 钲 荣*

Zhengrong Wang
Computer Science Department
University of California, Los Angeles
California, USA
90024

Work Email: [email protected]
Mobile :+1 310-447-4568
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