Hello Tony Gutierrez,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/29960
to review the following change.
Change subject: arch-gcn3: Remove invalid assert when reading EXEC_LO
......................................................................
arch-gcn3: Remove invalid assert when reading EXEC_LO
This assert assumed all reads to EXEC_LO would be
64b, that is, we would always read the entire EXEC
mask. This is invalid as some kernels read only
the low 32b of EXEC.
The write to EXEC_LO is also updated to handle 32b
writes.
Change-Id: Ifeb167578515bf112b1eab70bbf2201a5e936358
---
M src/arch/gcn3/operand.hh
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/arch/gcn3/operand.hh b/src/arch/gcn3/operand.hh
index 960d05e..9d28deb 100644
--- a/src/arch/gcn3/operand.hh
+++ b/src/arch/gcn3/operand.hh
@@ -435,9 +435,10 @@
if (!isScalarReg(_opIdx)) {
if (_opIdx == REG_EXEC_LO) {
- ScalarRegU64 new_exec_mask_val(0);
+ ScalarRegU64 new_exec_mask_val
+ = wf->execMask().to_ullong();
std::memcpy((void*)&new_exec_mask_val,
- (void*)srfData.data(), sizeof(new_exec_mask_val));
+ (void*)srfData.data(), sizeof(srfData));
VectorMask new_exec_mask(new_exec_mask_val);
wf->execMask() = new_exec_mask;
DPRINTF(GPUSRF, "Write EXEC\n");
@@ -513,7 +514,6 @@
switch(_opIdx) {
case REG_EXEC_LO:
{
- assert(NumDwords == 2);
ScalarRegU64 exec_mask = _gpuDynInst->wavefront()->
execMask().to_ullong();
std::memcpy((void*)srfData.data(), (void*)&exec_mask,
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ifeb167578515bf112b1eab70bbf2201a5e936358
Gerrit-Change-Number: 29960
Gerrit-PatchSet: 1
Gerrit-Owner: Anthony Gutierrez <[email protected]>
Gerrit-Reviewer: Tony Gutierrez <[email protected]>
Gerrit-MessageType: newchange
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