Hello Timothy Hayes,

I'd like you to do a code review. Please visit

    https://gem5-review.googlesource.com/c/public/gem5/+/30323

to review the following change.


Change subject: cpu: Add HTM ExecContext API
......................................................................

cpu: Add HTM ExecContext API

* initiateHtmCmd(Request::Flags flags)
* getHtmTransactionUid()
* newHtmTransactionUid()
* inHtmTransactionalState()
* getHtmTransactionalDepth()

JIRA: https://gem5.atlassian.net/browse/GEM5-587

Change-Id: I438832a3c47fff1d12d0123425985cfa2150ab40
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/cpu/base_dyn_inst.hh
M src/cpu/checker/cpu.hh
M src/cpu/exec_context.hh
M src/cpu/minor/exec_context.hh
M src/cpu/simple/exec_context.hh
5 files changed, 143 insertions(+), 0 deletions(-)



diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index b98cbaa..e1580a5 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -300,6 +300,8 @@
     Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags,
             const std::vector<bool>& byte_enable = std::vector<bool>());

+    Fault initiateHtmCmd(Request::Flags flags);
+
     Fault writeMem(uint8_t *data, unsigned size, Addr addr,
                    Request::Flags flags, uint64_t *res,
const std::vector<bool>& byte_enable = std::vector<bool>());
@@ -539,6 +541,30 @@
     bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
     bool isMicroBranch() const { return staticInst->isMicroBranch(); }

+    uint64_t getHtmTransactionUid() const override
+    {
+        panic("Not yet implemented\n");
+        return 0;
+    }
+
+    uint64_t newHtmTransactionUid() const override
+    {
+        panic("Not yet implemented\n");
+        return 0;
+    }
+
+    bool inHtmTransactionalState() const override
+    {
+        panic("Not yet implemented\n");
+        return false;
+    }
+
+    uint64_t getHtmTransactionalDepth() const override
+    {
+        panic("Not yet implemented\n");
+        return 0;
+    }
+
/** Temporarily sets this instruction as a serialize before instruction. */
     void setSerializeBefore() { status.set(SerializeBefore); }

@@ -964,6 +990,14 @@

 template<class Impl>
 Fault
+BaseDynInst<Impl>::initiateHtmCmd(Request::Flags flags)
+{
+    panic("Not yet implemented\n");
+    return NoFault;
+}
+
+template<class Impl>
+Fault
 BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, Addr addr,
                             Request::Flags flags, uint64_t *res,
                             const std::vector<bool>& byte_enable)
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 24fad1c..0e3ea2c 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -434,12 +434,36 @@
         thread->setMemAccPredicate(val);
     }

+    uint64_t getHtmTransactionUid() const override
+    {
+        panic("not yet supported!");
+        return 0;
+    };
+
+    uint64_t newHtmTransactionUid() const override
+    {
+        panic("not yet supported!");
+        return 0;
+    };
+
     Fault initiateHtmCmd(Request::Flags flags) override
     {
         panic("not yet supported!");
         return NoFault;
     }

+    bool inHtmTransactionalState() const override
+    {
+        panic("not yet supported!");
+        return false;
+    }
+
+    uint64_t getHtmTransactionalDepth() const override
+    {
+        panic("not yet supported!");
+        return 0;
+    }
+
     TheISA::PCState pcState() const override { return thread->pcState(); }
     void
     pcState(const TheISA::PCState &val) override
diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh
index 29daced..2492c4b 100644
--- a/src/cpu/exec_context.hh
+++ b/src/cpu/exec_context.hh
@@ -253,6 +253,11 @@
     }

     /**
+     * Initiate an HTM command,
+     * e.g. tell Ruby we're starting/stopping a transaction
+     */
+    virtual Fault initiateHtmCmd(Request::Flags flags) = 0;
+    /**
      * For atomic-mode contexts, perform an atomic memory write operation.
      * For timing-mode contexts, initiate a timing memory write operation.
      */
@@ -320,6 +325,12 @@
     virtual bool readMemAccPredicate() const = 0;
     virtual void setMemAccPredicate(bool val) = 0;

+    // hardware transactional memory
+    virtual uint64_t newHtmTransactionUid() const = 0;
+    virtual uint64_t getHtmTransactionUid() const = 0;
+    virtual bool inHtmTransactionalState() const = 0;
+    virtual uint64_t getHtmTransactionalDepth() const = 0;
+
     /** @} */

     /**
diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh
index a0b1d18..4ff046a 100644
--- a/src/cpu/minor/exec_context.hh
+++ b/src/cpu/minor/exec_context.hh
@@ -114,6 +114,13 @@
     }

     Fault
+    initiateHtmCmd(Request::Flags flags) override
+    {
+ panic("ExecContext::initiateHtmCmd() not implemented on MinorCPU\n");
+        return NoFault;
+    }
+
+    Fault
     writeMem(uint8_t *data, unsigned int size, Addr addr,
              Request::Flags flags, uint64_t *res,
              const std::vector<bool>& byte_enable = std::vector<bool>())
@@ -333,6 +340,39 @@
         thread.setMemAccPredicate(val);
     }

+    // hardware transactional memory
+    uint64_t
+    getHtmTransactionUid() const override
+    {
+        panic("ExecContext::getHtmTransactionUid() not"
+              "implemented on MinorCPU\n");
+        return 0;
+    }
+
+    uint64_t
+    newHtmTransactionUid() const override
+    {
+        panic("ExecContext::newHtmTransactionUid() not"
+              "implemented on MinorCPU\n");
+        return 0;
+    }
+
+    bool
+    inHtmTransactionalState() const override
+    {
+        // ExecContext::inHtmTransactionalState() not
+        // implemented on MinorCPU
+        return false;
+    }
+
+    uint64_t
+    getHtmTransactionalDepth() const override
+    {
+        panic("ExecContext::getHtmTransactionalDepth() not"
+              "implemented on MinorCPU\n");
+        return 0;
+    }
+
     TheISA::PCState
     pcState() const override
     {
diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh
index e7c59c0..ade9b68 100644
--- a/src/cpu/simple/exec_context.hh
+++ b/src/cpu/simple/exec_context.hh
@@ -473,6 +473,12 @@
         return cpu->initiateMemAMO(addr, size, flags, std::move(amo_op));
     }

+    Fault initiateHtmCmd(Request::Flags flags) override
+    {
+        panic("Not yet supported\n");
+        return NoFault;
+    }
+
     /**
      * Sets the number of consecutive store conditional failures.
      */
@@ -531,6 +537,34 @@
         thread->setMemAccPredicate(val);
     }

+    uint64_t
+    getHtmTransactionUid() const override
+    {
+        panic("Not yet supported\n");
+        return 0;
+    }
+
+    uint64_t
+    newHtmTransactionUid() const override
+    {
+        panic("Not yet supported\n");
+        return 0;
+    }
+
+    bool
+    inHtmTransactionalState() const override
+    {
+        panic("Not yet supported\n");
+        return false;
+    }
+
+    uint64_t
+    getHtmTransactionalDepth() const override
+    {
+        panic("Not yet supported\n");
+        return 0;
+    }
+
     /**
      * Invalidate a page in the DTLB <i>and</i> ITLB.
      */

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/30323
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I438832a3c47fff1d12d0123425985cfa2150ab40
Gerrit-Change-Number: 30323
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Timothy Hayes <timothy.ha...@arm.com>
Gerrit-MessageType: newchange
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