Jordi Vaquero has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/30619 )
Change subject: arch-arm: Add Check for AddressSize Fault
......................................................................
arch-arm: Add Check for AddressSize Fault
This patch add a check for AddressSize Fault during translation when
MMU is disabled.
Change-Id: Iff3a1543df010b086813869b4b6c4fe776e74499
---
M src/arch/arm/tlb.cc
1 file changed, 18 insertions(+), 0 deletions(-)
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index a00cba8..8a6e684 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -1011,12 +1011,30 @@
TLB::ArmTranslationType tranType, Addr vaddr, bool
long_desc_format)
{
bool is_fetch = (mode == Execute);
+ bool is_atomic = req->isAtomic();
req->setPaddr(vaddr);
// When the MMU is off the security attribute corresponds to the
// security state of the processor
if (isSecure)
req->setFlags(Request::SECURE);
+ bool selbit = bits(vaddr, 55);
+ TCR tcr1 = tc->readMiscReg(MISCREG_TCR_EL1);
+ int topbit = computeAddrTop(tc, selbit, is_fetch, tcr1, currEL(tc));
+ int addr_sz = bits(vaddr, topbit, MaxPhysAddrRange);
+ if (addr_sz != 0){
+ Fault f;
+ if (is_fetch)
+ f = std::make_shared<PrefetchAbort>(vaddr,
+ ArmFault::AddressSizeLL, isStage2, ArmFault::LpaeTran);
+ else
+ f = std::make_shared<DataAbort>( vaddr,
+ TlbEntry::DomainType::NoAccess,
+ is_atomic ? false : mode==Write,
+ ArmFault::AddressSizeLL, isStage2, ArmFault::LpaeTran);
+ return f;
+ }
+
// @todo: double check this (ARM ARM issue C B3.2.1)
if (long_desc_format || sctlr.tre == 0 || nmrr.ir0 == 0 ||
nmrr.or0 == 0 || prrr.tr0 != 0x2) {
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iff3a1543df010b086813869b4b6c4fe776e74499
Gerrit-Change-Number: 30619
Gerrit-PatchSet: 1
Gerrit-Owner: Jordi Vaquero <[email protected]>
Gerrit-MessageType: newchange
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