[gem5-dev] Change in gem5/gem5[develop]: cpu: Some cleanups in the O3 rename map.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/30454 )

Change subject: cpu: Some cleanups in the O3 rename map.
......................................................................
cpu: Some cleanups in the O3 rename map.

Fix some style problems, mostly having to do with return type, but also
one with indentation.

Also simplify the very nested set of std::min-s into one.

Change-Id: I6dbb22128755d5b0c6bb71bd6f1b01e6234e2377
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30454
Reviewed-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/cpu/o3/rename_map.hh
1 file changed, 21 insertions(+), 14 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/cpu/o3/rename_map.hh b/src/cpu/o3/rename_map.hh
index 1196af2..22bca56 100644
--- a/src/cpu/o3/rename_map.hh
+++ b/src/cpu/o3/rename_map.hh
@@ -121,7 +121,8 @@
      * @param arch_reg The architectural register to look up.
      * @return The physical register it is currently mapped to.
      */
-    PhysRegIdPtr lookup(const RegId& arch_reg) const
+    PhysRegIdPtr
+    lookup(const RegId& arch_reg) const
     {
         assert(arch_reg.flatIndex() <= map.size());
         return map[arch_reg.flatIndex()];
@@ -133,7 +134,8 @@
      * @param arch_reg The architectural register to remap.
      * @param phys_reg The physical register to remap it to.
      */
-    void setEntry(const RegId& arch_reg, PhysRegIdPtr phys_reg)
+    void
+    setEntry(const RegId& arch_reg, PhysRegIdPtr phys_reg)
     {
         assert(arch_reg.flatIndex() <= map.size());
         map[arch_reg.flatIndex()] = phys_reg;
@@ -262,7 +264,8 @@
      * @param arch_reg The architectural register to look up.
      * @return The physical register it is currently mapped to.
      */
-    PhysRegIdPtr lookup(const RegId& arch_reg) const
+    PhysRegIdPtr
+    lookup(const RegId& arch_reg) const
     {
         switch (arch_reg.classValue()) {
           case IntRegClass:
@@ -304,7 +307,8 @@
      * @param arch_reg The architectural register to remap.
      * @param phys_reg The physical register to remap it to.
      */
-    void setEntry(const RegId& arch_reg, PhysRegIdPtr phys_reg)
+    void
+    setEntry(const RegId& arch_reg, PhysRegIdPtr phys_reg)
     {
         switch (arch_reg.classValue()) {
           case IntRegClass:
@@ -353,18 +357,20 @@
      * this number of entries is available regardless of which class
      * of registers is requested.
      */
-    unsigned numFreeEntries() const
+    unsigned
+    numFreeEntries() const
     {
-        return std::min(std::min(
-                std::min(intMap.numFreeEntries(),  
floatMap.numFreeEntries()),
-                vecMode == Enums::Full ? vecMap.numFreeEntries()
-                                    : vecElemMap.numFreeEntries()),
-                predMap.numFreeEntries());
+        return std::min({intMap.numFreeEntries(),
+                         floatMap.numFreeEntries(),
+                         vecMode == Enums::Full ? vecMap.numFreeEntries() :
+                                                   
vecElemMap.numFreeEntries(),
+                         predMap.numFreeEntries()});
     }

     unsigned numFreeIntEntries() const { return intMap.numFreeEntries(); }
     unsigned numFreeFloatEntries() const { return  
floatMap.numFreeEntries(); }
-    unsigned numFreeVecEntries() const
+    unsigned
+    numFreeVecEntries() const
     {
         return vecMode == Enums::Full
                 ? vecMap.numFreeEntries()
@@ -376,9 +382,10 @@
     /**
      * Return whether there are enough registers to serve the request.
      */
-    bool canRename(uint32_t intRegs, uint32_t floatRegs, uint32_t  
vectorRegs,
-                   uint32_t vecElemRegs, uint32_t vecPredRegs,
-                   uint32_t ccRegs) const
+    bool
+    canRename(uint32_t intRegs, uint32_t floatRegs, uint32_t vectorRegs,
+              uint32_t vecElemRegs, uint32_t vecPredRegs,
+              uint32_t ccRegs) const
     {
         return intRegs <= intMap.numFreeEntries() &&
             floatRegs <= floatMap.numFreeEntries() &&

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6dbb22128755d5b0c6bb71bd6f1b01e6234e2377
Gerrit-Change-Number: 30454
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black <gabebl...@google.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Bobby R. Bruce <bbr...@ucdavis.edu>
Gerrit-Reviewer: Gabe Black <gabebl...@google.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Jason Lowe-Power <power...@gmail.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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