Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31055 )
Change subject: dev-arm: Use getIntConfig when reading/writing GICD_ICFGR
......................................................................
dev-arm: Use getIntConfig when reading/writing GICD_ICFGR
This patch is changing the getIntConfig helper (which has been
used so far by isLevelSensitive only) to make it usable by the
read/writes of the GICD_ICFGR register.
While the helper was previously returning the irq config bits
provided a single irq as an input, this new version is returning
the entire GICD_ICFGR word (read/writable)
JIRA: https://gem5.atlassian.net/browse/GEM5-667
Change-Id: I07e455a9e2819fed1f97a0e372d9d9a2e5ad4801
Signed-off-by: Giacomo Travaglini <[email protected]>
---
M src/dev/arm/gic_v2.cc
M src/dev/arm/gic_v2.hh
2 files changed, 16 insertions(+), 18 deletions(-)
diff --git a/src/dev/arm/gic_v2.cc b/src/dev/arm/gic_v2.cc
index 4ef1517..302da2f 100644
--- a/src/dev/arm/gic_v2.cc
+++ b/src/dev/arm/gic_v2.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010, 2013, 2015-2018 ARM Limited
+ * Copyright (c) 2010, 2013, 2015-2018, 2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -72,7 +72,7 @@
enabled(false), haveGem5Extensions(p->gem5_extensions),
itLines(p->it_lines),
intEnabled {}, pendingInt {}, activeInt {},
- intPriority {}, cpuTarget {}, intConfig {},
+ intPriority {}, intConfig {}, cpuTarget {},
cpuSgiPending {}, cpuSgiActive {},
cpuSgiPendingExt {}, cpuSgiActiveExt {},
cpuPpiPending {}, cpuPpiActive {},
@@ -250,10 +250,7 @@
if (GICD_ICFGR.contains(daddr)) {
uint32_t ix = (daddr - GICD_ICFGR.start()) >> 2;
- assert(ix < 64);
- /** @todo software generated interrupts and PPIs
- * can't be configured in some ways */
- return intConfig[ix];
+ return getIntConfig(ctx, ix);
}
switch(daddr) {
@@ -521,8 +518,7 @@
if (GICD_ICFGR.contains(daddr)) {
uint32_t ix = (daddr - GICD_ICFGR.start()) >> 2;
- assert(ix < INT_BITS_MAX*2);
- intConfig[ix] = data;
+ getIntConfig(ctx, ix) = data;
if (data & NN_CONFIG_MASK)
warn("GIC N:N mode selected and not supported at this time\n");
return;
diff --git a/src/dev/arm/gic_v2.hh b/src/dev/arm/gic_v2.hh
index 40a9553..aefa938 100644
--- a/src/dev/arm/gic_v2.hh
+++ b/src/dev/arm/gic_v2.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010, 2013, 2015-2019 ARM Limited
+ * Copyright (c) 2010, 2013, 2015-2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -286,13 +286,13 @@
uint32_t intConfig[INT_BITS_MAX*2];
/** GICD_ICFGRn
- * get 2 bit config associated to an interrupt.
+ * @param ctx context id (PE specific)
+ * @param ix interrupt word index
+ * @returns the interrupt config word
*/
- uint8_t getIntConfig(ContextID ctx, uint32_t ix) {
- assert(ix < INT_LINES_MAX);
- const uint8_t cfg_low = intNumToBit(ix * 2);
- const uint8_t cfg_hi = cfg_low + 1;
- return bits(intConfig[intNumToWord(ix * 2)], cfg_hi, cfg_low);
+ uint32_t& getIntConfig(ContextID ctx, uint32_t ix) {
+ assert(ix < INT_BITS_MAX*2);
+ return intConfig[ix];
}
/** GICD_ITARGETSR{8..255}
@@ -323,11 +323,13 @@
}
}
- bool isLevelSensitive(ContextID ctx, uint32_t ix) {
- if (ix == SPURIOUS_INT) {
+ bool isLevelSensitive(ContextID ctx, uint32_t int_num) {
+ if (int_num == SPURIOUS_INT) {
return false;
} else {
- return bits(getIntConfig(ctx, ix), 1) == 0;
+ const auto ix = intNumToWord(int_num * 2);
+ const uint8_t cfg_hi = intNumToBit(int_num * 2) + 1;
+ return bits(getIntConfig(ctx, ix), cfg_hi) == 0;
}
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I07e455a9e2819fed1f97a0e372d9d9a2e5ad4801
Gerrit-Change-Number: 31055
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-MessageType: newchange
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