Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31269 )
Change subject: mem-ruby: sequencer callback for unique writes
......................................................................
mem-ruby: sequencer callback for unique writes
A controller may complete a write without obtaining a full copy of
the line. This patch adds a specific callback for this purpose that
prevents reads to be coalesced with a write on a potentially incomplete
line.
Change-Id: I3775f81699f38e406fee28f92c9c8e06deb3d528
Signed-off-by: Tiago Mück <tiago.m...@arm.com>
---
M src/mem/ruby/protocol/RubySlicc_Types.sm
M src/mem/ruby/system/Sequencer.cc
M src/mem/ruby/system/Sequencer.hh
3 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/src/mem/ruby/protocol/RubySlicc_Types.sm
b/src/mem/ruby/protocol/RubySlicc_Types.sm
index adbe06e..cb24d3a 100644
--- a/src/mem/ruby/protocol/RubySlicc_Types.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Types.sm
@@ -129,6 +129,7 @@
void writeCallback(Addr, DataBlock, bool, MachineType);
void writeCallback(Addr, DataBlock, bool, MachineType,
Cycles, Cycles, Cycles);
+ void writeUniqueCallback(Addr, DataBlock);
// ll/sc support
void writeCallbackScFail(Addr, DataBlock);
diff --git a/src/mem/ruby/system/Sequencer.cc
b/src/mem/ruby/system/Sequencer.cc
index b6b1ae3..d7c3e15 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -340,7 +340,8 @@
const bool externalHit, const MachineType mach,
const Cycles initialRequestTime,
const Cycles forwardRequestTime,
- const Cycles firstResponseTime)
+ const Cycles firstResponseTime,
+ const bool noCoales)
{
//
// Free the whole list as we assume we have had the exclusive access
@@ -358,6 +359,15 @@
int aliased_loads = 0;
while (!seq_req_list.empty()) {
SequencerRequest &seq_req = seq_req_list.front();
+
+ if (noCoales && !ruby_request) {
+ // Do not process follow-up requests
+ // (e.g. if full line no present)
+ // Reissue to the cache hierarchy
+ issueRequest(seq_req.pkt, seq_req.m_second_type);
+ break;
+ }
+
if (ruby_request) {
assert(seq_req.m_type != RubyRequestType_LD);
assert(seq_req.m_type != RubyRequestType_Load_Linked);
diff --git a/src/mem/ruby/system/Sequencer.hh
b/src/mem/ruby/system/Sequencer.hh
index 594b4f7..b4da03f 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -103,7 +103,15 @@
const MachineType mach = MachineType_NUM,
const Cycles initialRequestTime = Cycles(0),
const Cycles forwardRequestTime = Cycles(0),
- const Cycles firstResponseTime = Cycles(0));
+ const Cycles firstResponseTime = Cycles(0),
+ const bool noCoales = false);
+
+ // Write callback that prevents coalescing
+ void writeUniqueCallback(Addr address, DataBlock& data)
+ {
+ writeCallback(address, data, true, MachineType_NUM, Cycles(0),
+ Cycles(0), Cycles(0), true);
+ }
void readCallback(Addr address,
DataBlock& data,
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3775f81699f38e406fee28f92c9c8e06deb3d528
Gerrit-Change-Number: 31269
Gerrit-PatchSet: 1
Gerrit-Owner: Tiago Mück <tiago.m...@arm.com>
Gerrit-MessageType: newchange
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