Hello Richard Cooper,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/31354
to review the following change.
Change subject: arch-arm: Reduce boilerplate when extracting SelfDebug from
tc
......................................................................
arch-arm: Reduce boilerplate when extracting SelfDebug from tc
Change-Id: I1746400617be64ac9c2f3194442734e178342909
Signed-off-by: Giacomo Travaglini <[email protected]>
Reviewed-by: Richard Cooper <[email protected]>
---
M src/arch/arm/faults.cc
M src/arch/arm/insts/pseudo.cc
M src/arch/arm/insts/static_inst.cc
M src/arch/arm/insts/static_inst.hh
M src/arch/arm/isa.hh
M src/arch/arm/isa/insts/ldr.isa
M src/arch/arm/isa/insts/ldr64.isa
M src/arch/arm/tlb.cc
8 files changed, 28 insertions(+), 23 deletions(-)
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 743e08d..6009bfc 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -723,8 +723,7 @@
bool
ArmFault::vectorCatch(ThreadContext *tc, const StaticInstPtr &inst)
{
- auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
- SelfDebug * sd = isa->getSelfDebug();
+ SelfDebug *sd = ArmISA::ISA::getSelfDebug(tc);
VectorCatch* vc = sd->getVectorCatch(tc);
if (!vc->isVCMatch()) {
Fault fault = sd->testVectorCatch(tc, 0x0, this);
diff --git a/src/arch/arm/insts/pseudo.cc b/src/arch/arm/insts/pseudo.cc
index 3fe2dfa..bf1fecc 100644
--- a/src/arch/arm/insts/pseudo.cc
+++ b/src/arch/arm/insts/pseudo.cc
@@ -201,8 +201,11 @@
PCState pc_state(xc->pcState());
pc_state.debugStep(false);
xc->pcState(pc_state);
- auto *isa = static_cast<ArmISA::ISA *>(xc->tcBase()->getIsaPtr());
- bool ldx = isa->getSelfDebug()->getSstep()->getLdx();
+
+ SelfDebug *sd = ArmISA::ISA::getSelfDebug(xc->tcBase());
+
+ bool ldx = sd->getSstep()->getLdx();
+
return std::make_shared<SoftwareStepFault>(machInst, ldx,
pc_state.stepped());
diff --git a/src/arch/arm/insts/static_inst.cc
b/src/arch/arm/insts/static_inst.cc
index f188987..82c6b4e 100644
--- a/src/arch/arm/insts/static_inst.cc
+++ b/src/arch/arm/insts/static_inst.cc
@@ -1155,8 +1155,8 @@
new_cpsr.daif = spsr.daif;
}
- auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
- SoftwareStep * ss = (isa->getSelfDebug())->getSstep();
+ SelfDebug *sd = ArmISA::ISA::getSelfDebug(tc);
+ SoftwareStep *ss = sd->getSstep();
new_cpsr.ss = ss->debugExceptionReturnSS(tc, spsr, dest,
new_cpsr.width);
return new_cpsr;
diff --git a/src/arch/arm/insts/static_inst.hh
b/src/arch/arm/insts/static_inst.hh
index 8610f99..2b30d74 100644
--- a/src/arch/arm/insts/static_inst.hh
+++ b/src/arch/arm/insts/static_inst.hh
@@ -203,8 +203,7 @@
static void
activateBreakpoint(ThreadContext *tc)
{
- auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
- SelfDebug * sd = isa->getSelfDebug();
+ SelfDebug *sd = ArmISA::ISA::getSelfDebug(tc);
sd->activateDebug();
}
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index be57f41..cd77215 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -465,10 +465,19 @@
void initID64(const ArmISAParams *p);
public:
- SelfDebug * getSelfDebug()
+ SelfDebug*
+ getSelfDebug() const
{
return selfDebug;
}
+
+ static SelfDebug*
+ getSelfDebug(ThreadContext *tc)
+ {
+ auto *arm_isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
+ return arm_isa->getSelfDebug();
+ }
+
RegVal readMiscRegNoEffect(int misc_reg) const;
RegVal readMiscReg(int misc_reg);
void setMiscRegNoEffect(int misc_reg, RegVal val);
diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa
index 37abb64..d7e27a4 100644
--- a/src/arch/arm/isa/insts/ldr.isa
+++ b/src/arch/arm/isa/insts/ldr.isa
@@ -211,9 +211,8 @@
if self.flavor in ('exclusive', 'acex'):
accCode += '''
- auto *isa = static_cast<ArmISA::ISA
*>(xc->tcBase()->getIsaPtr());
- SelfDebug * sd = isa->getSelfDebug();
- sd->getSstep()->setLdx();
+ SelfDebug *sd = ArmISA::ISA::getSelfDebug(xc->tcBase());
+ sd->getSstep()->setLdx();
'''
self.codeBlobs["memacc_code"] = accCode
@@ -293,9 +292,8 @@
'''
if self.flavor in ('exclusive', 'acex'):
accCode += '''
- auto *isa = static_cast<ArmISA::ISA
*>(xc->tcBase()->getIsaPtr());
- SelfDebug * sd = isa->getSelfDebug();
- sd->getSstep()->setLdx();
+ SelfDebug *sd = ArmISA::ISA::getSelfDebug(xc->tcBase());
+ sd->getSstep()->setLdx();
'''
self.codeBlobs["memacc_code"] = accCode
diff --git a/src/arch/arm/isa/insts/ldr64.isa
b/src/arch/arm/isa/insts/ldr64.isa
index a2c1bae..de4c5f7 100644
--- a/src/arch/arm/isa/insts/ldr64.isa
+++ b/src/arch/arm/isa/insts/ldr64.isa
@@ -238,9 +238,8 @@
accCode = accCode % buildMemSuffix(self.sign, self.size)
if self.flavor in ('exclusive', 'acex'):
accCode += '''
- auto *isa = static_cast<ArmISA::ISA
*>(xc->tcBase()->getIsaPtr());
- SelfDebug * sd = isa->getSelfDebug();
- sd->getSstep()->setLdx();
+ SelfDebug *sd = ArmISA::ISA::getSelfDebug(xc->tcBase());
+ sd->getSstep()->setLdx();
'''
self.codeBlobs["memacc_code"] = accCode
if accEpilogCode:
@@ -339,9 +338,8 @@
'''
if self.flavor in ('exp', 'acexp'):
accCode += '''
- auto *isa = static_cast<ArmISA::ISA
*>(xc->tcBase()->getIsaPtr());
- SelfDebug * sd = isa->getSelfDebug();
- sd->getSstep()->setLdx();
+ SelfDebug *sd = ArmISA::ISA::getSelfDebug(xc->tcBase());
+ sd->getSstep()->setLdx();
'''
self.codeBlobs["memacc_code"] = accCode
if accEpilogCode:
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index ca97849..8de1069 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -1214,8 +1214,7 @@
//Check for Debug Exceptions
if (fault == NoFault) {
- auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
- SelfDebug *sd = isa->getSelfDebug();
+ SelfDebug *sd = ArmISA::ISA::getSelfDebug(tc);
fault = sd->testDebug(tc, req, mode);
}
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31354
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I1746400617be64ac9c2f3194442734e178342909
Gerrit-Change-Number: 31354
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Richard Cooper <[email protected]>
Gerrit-MessageType: newchange
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