Hello Nikos Nikoleris,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/31515
to review the following change.
Change subject: dev-arm: Implement LevelSensitive SPIs in GICv3
......................................................................
dev-arm: Implement LevelSensitive SPIs in GICv3
Change-Id: If918a8aea934f0037818cc64bf458076bfd0251d
Signed-off-by: Giacomo Travaglini <[email protected]>
Reviewed-by: Nikos Nikoleris <[email protected]>
---
M src/dev/arm/gic_v3.cc
M src/dev/arm/gic_v3_distributor.cc
M src/dev/arm/gic_v3_distributor.hh
3 files changed, 25 insertions(+), 6 deletions(-)
diff --git a/src/dev/arm/gic_v3.cc b/src/dev/arm/gic_v3.cc
index 5751940..8e75b1c 100644
--- a/src/dev/arm/gic_v3.cc
+++ b/src/dev/arm/gic_v3.cc
@@ -177,9 +177,10 @@
}
void
-Gicv3::clearInt(uint32_t number)
+Gicv3::clearInt(uint32_t int_id)
{
- distributor->deassertSPI(number);
+ DPRINTF(Interrupt, "Gicv3::clearInt(): received SPI %d\n", int_id);
+ distributor->clearInt(int_id);
}
void
diff --git a/src/dev/arm/gic_v3_distributor.cc
b/src/dev/arm/gic_v3_distributor.cc
index 485ba72..f54c02f 100644
--- a/src/dev/arm/gic_v3_distributor.cc
+++ b/src/dev/arm/gic_v3_distributor.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019 ARM Limited
+ * Copyright (c) 2019-2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -1001,6 +1001,16 @@
}
void
+Gicv3Distributor::clearInt(uint32_t int_id)
+{
+ // Edge-triggered interrupts remain pending until software
+ // writes GICD_ICPENDR, GICD_CLRSPI_* or activates them via ICC_IAR
+ if (isLevelSensitive(int_id)) {
+ deassertSPI(int_id);
+ }
+}
+
+void
Gicv3Distributor::deassertSPI(uint32_t int_id)
{
panic_if(int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX, "Invalid SPI!");
@@ -1140,7 +1150,9 @@
void
Gicv3Distributor::activateIRQ(uint32_t int_id)
{
- irqPending[int_id] = false;
+ if (!isLevelSensitive(int_id)) {
+ irqPending[int_id] = false;
+ }
irqActive[int_id] = true;
}
diff --git a/src/dev/arm/gic_v3_distributor.hh
b/src/dev/arm/gic_v3_distributor.hh
index 62bed18..edcfd42 100644
--- a/src/dev/arm/gic_v3_distributor.hh
+++ b/src/dev/arm/gic_v3_distributor.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019 ARM Limited
+ * Copyright (c) 2019-2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -222,6 +222,11 @@
}
}
+ bool isLevelSensitive(uint32_t int_id) const
+ {
+ return irqConfig[int_id] == Gicv3::INT_LEVEL_SENSITIVE;
+ }
+
inline bool nsAccessToSecInt(uint32_t int_id, bool is_secure_access)
const
{
return !DS && !is_secure_access && getIntGroup(int_id) !=
Gicv3::G1NS;
@@ -236,11 +241,12 @@
Gicv3Distributor(Gicv3 * gic, uint32_t it_lines);
+ void sendInt(uint32_t int_id);
+ void clearInt(uint32_t int_id);
void deassertSPI(uint32_t int_id);
void clearIrqCpuInterface(uint32_t int_id);
void init();
uint64_t read(Addr addr, size_t size, bool is_secure_access);
- void sendInt(uint32_t int_id);
void write(Addr addr, uint64_t data, size_t size,
bool is_secure_access);
};
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31515
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If918a8aea934f0037818cc64bf458076bfd0251d
Gerrit-Change-Number: 31515
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Nikos Nikoleris <[email protected]>
Gerrit-MessageType: newchange
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