Jordi Vaquero has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31374 )
Change subject: arch-arm: Fix Fault subsystem adding EL2Enable func
......................................................................
arch-arm: Fix Fault subsystem adding EL2Enable func
Change-Id: I7a4f0c22ac31fd56a8976ee8a1d9760cf6055d63
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31374
Reviewed-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/arch/arm/faults.cc
M src/arch/arm/faults.hh
2 files changed, 58 insertions(+), 57 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 743e08d..40cf634 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -819,17 +819,9 @@
bool
UndefinedInstruction::routeToHyp(ThreadContext *tc) const
{
- bool toHyp;
-
- SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
- CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
-
- // if in Hyp mode then stay in Hyp mode
- toHyp = scr.ns && (currEL(tc) == EL2);
- // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
- toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (currEL(tc) == EL0);
- return toHyp;
+ return fromEL == EL2 ||
+ (EL2Enabled(tc) && (fromEL == EL0) && hcr.tge);
}
uint32_t
@@ -885,7 +877,8 @@
SupervisorCall::routeToHyp(ThreadContext *tc) const
{
HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
- return EL2Enabled(tc) && currEL(tc) == EL0 && hcr.tge == 1;
+ return fromEL == EL2 ||
+ (EL2Enabled(tc) && fromEL == EL0 && hcr.tge);
}
ExceptionClass
@@ -929,6 +922,18 @@
bStep = true;
}
+bool
+HypervisorCall::routeToMonitor(ThreadContext *tc) const
+{
+ return from64 && fromEL == EL3;
+}
+
+bool
+HypervisorCall::routeToHyp(ThreadContext *tc) const
+{
+ return !from64 || fromEL != EL3;
+}
+
ExceptionClass
HypervisorCall::ec(ThreadContext *tc) const
{
@@ -1301,20 +1306,14 @@
{
bool toHyp;
- SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
HDCR hdcr = tc->readMiscRegNoEffect(MISCREG_HDCR);
- // if in Hyp mode then stay in Hyp mode
- toHyp = scr.ns && (currEL(tc) == EL2);
- toHyp |= (currEL(tc) <= EL1) && hcr.tge;
- // otherwise, check whether to take to Hyp mode through Hyp Trap vector
- toHyp |= (stage2 ||
- ((source == DebugEvent) && (hdcr.tde || hcr.tge) &&
- (currEL(tc) != EL2)) ||
- ((source == SynchronousExternalAbort) && hcr.tge &&
- (currEL(tc) == EL0))) && !inSecureState(tc);
- return toHyp;
+ toHyp = fromEL == EL2;
+ toHyp |= ArmSystem::haveEL(tc, EL2) && !inSecureState(tc) &&
+ currEL(tc) <= EL1 && (hcr.tge || stage2 ||
+ (source == DebugEvent && hdcr.tde));
+ return toHyp;
}
ExceptionClass
@@ -1363,21 +1362,22 @@
{
bool toHyp;
- SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
HDCR hdcr = tc->readMiscRegNoEffect(MISCREG_HDCR);
+ bool amo = hcr.amo;
+ if (hcr.tge == 1)
+ amo = (!HaveVirtHostExt(tc) || hcr.e2h == 0);
+
// if in Hyp mode then stay in Hyp mode
- toHyp = scr.ns && (currEL(tc) == EL2);
- toHyp |= (currEL(tc) <= EL1 && hcr.tge==1);
- // otherwise, check whether to take to Hyp mode through Hyp Trap vector
- toHyp |= (stage2 ||
- ((currEL(tc) != EL2) &&
- (((source == AsynchronousExternalAbort) && hcr.amo) ||
- ((source == DebugEvent) && (hdcr.tde || hcr.tge)))) ||
- ((currEL(tc) == EL0) && hcr.tge &&
- ((source == AlignmentFault) ||
- (source == SynchronousExternalAbort))))
&& !inSecureState(tc);
+ toHyp = fromEL == EL2 ||
+ (EL2Enabled(tc) && fromEL <= EL1
+ && (hcr.tge || stage2 ||
+ ((source == AsynchronousExternalAbort) && amo) ||
+ ((fromEL == EL0) && hcr.tge &&
+ ((source == AlignmentFault) ||
+ (source == SynchronousExternalAbort))) ||
+ ((source == DebugEvent) && (hdcr.tde || hcr.tge))));
return toHyp;
}
@@ -1472,7 +1472,7 @@
{
HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
return fromEL == EL2 ||
- (EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge == 1 || hcr.imo));
+ (EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge || hcr.imo));
}
bool
@@ -1505,7 +1505,7 @@
{
HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
return fromEL == EL2 ||
- (EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge == 1 || hcr.fmo));
+ (EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge || hcr.fmo));
}
bool
@@ -1546,7 +1546,7 @@
PCAlignmentFault::routeToHyp(ThreadContext *tc) const
{
HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
- return EL2Enabled(tc) && currEL(tc) <= EL1 && hcr.tge == 1;
+ return fromEL == EL2 || (EL2Enabled(tc) && fromEL <= EL1 && hcr.tge);
}
SPAlignmentFault::SPAlignmentFault()
@@ -1576,21 +1576,18 @@
assert(ArmSystem::haveSecurity(tc));
assert(from64);
SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
- return scr.ea;
+ return scr.ea || fromEL == EL3;
}
bool
SystemError::routeToHyp(ThreadContext *tc) const
{
- bool toHyp;
assert(from64);
- SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
- HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
+ HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
- toHyp = (!scr.ea && hcr.amo && !inSecureState(tc)) ||
- (!scr.ea && !scr.rw && !hcr.amo && !inSecureState(tc));
- return toHyp;
+ return fromEL == EL2 ||
+ (EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge || hcr.amo));
}
@@ -1601,13 +1598,11 @@
bool
SoftwareBreakpoint::routeToHyp(ThreadContext *tc) const
{
- const bool have_el2 = ArmSystem::haveVirtualization(tc);
-
const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
- return have_el2 && !inSecureState(tc) && fromEL <= EL1 &&
- (hcr.tge || mdcr.tde);
+ return fromEL == EL2 ||
+ (EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge || mdcr.tde));
}
ExceptionClass
@@ -1623,13 +1618,10 @@
bool
HardwareBreakpoint::routeToHyp(ThreadContext *tc) const
{
- const bool have_el2 = ArmSystem::haveVirtualization(tc);
-
const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
- return have_el2 && !inSecureState(tc) && fromEL <= EL1 &&
- (hcr.tge || mdcr.tde);
+ return EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge || mdcr.tde);
}
ExceptionClass
@@ -1704,8 +1696,8 @@
const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
- return fromEL == EL2 || (EL2Enabled(tc) && fromEL <= EL1 &&
- (hcr.tge || mdcr.tde));
+ return fromEL == EL2 ||
+ (EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge || mdcr.tde));
}
void
@@ -1744,13 +1736,11 @@
bool
SoftwareStepFault::routeToHyp(ThreadContext *tc) const
{
- const bool have_el2 = ArmSystem::haveVirtualization(tc);
-
const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
- return have_el2 && !inSecureState(tc) && fromEL <= EL1 &&
- (hcr.tge || mdcr.tde);
+ return fromEL == EL2 ||
+ (EL2Enabled(tc) && fromEL <= EL1 && (hcr.tge || mdcr.tde));
}
ExceptionClass
@@ -1825,6 +1815,13 @@
{}
bool
+IllegalInstSetStateFault::routeToHyp(ThreadContext *tc) const
+{
+ const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
+ return EL2Enabled(tc) && fromEL == EL0 && hcr.tge;
+}
+
+bool
getFaultVAddr(Fault fault, Addr &va)
{
auto arm_fault = dynamic_cast<ArmFault *>(fault.get());
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index 7a2f69e..b911136 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -406,6 +406,8 @@
public:
HypervisorCall(ExtMachInst _machInst, uint32_t _imm);
+ bool routeToHyp(ThreadContext *tc) const override;
+ bool routeToMonitor(ThreadContext *tc) const override;
ExceptionClass ec(ThreadContext *tc) const override;
uint32_t vectorCatchFlag() const override { return 0xFFFFFFFF; }
};
@@ -677,6 +679,8 @@
{
public:
IllegalInstSetStateFault();
+
+ bool routeToHyp(ThreadContext *tc) const override;
};
/*
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7a4f0c22ac31fd56a8976ee8a1d9760cf6055d63
Gerrit-Change-Number: 31374
Gerrit-PatchSet: 10
Gerrit-Owner: Jordi Vaquero <jordi.vaqu...@metempsy.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Jordi Vaquero <jordi.vaqu...@metempsy.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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