[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add System register trap check for EL1

[Jordi Vaquero (Gerrit) via gem5-dev]

Jordi Vaquero has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/31694 )

Change subject: arch-arm: Add System register trap check for EL1
......................................................................

arch-arm: Add System register trap check for EL1

Change-Id: Ief3e0a9f70cc8cd44c1c8215515f36168927362d
---
M src/arch/arm/insts/misc64.cc
M src/arch/arm/miscregs_types.hh
2 files changed, 27 insertions(+), 0 deletions(-)



diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc
index 51e6028..cd6386a 100644
--- a/src/arch/arm/insts/misc64.cc
+++ b/src/arch/arm/insts/misc64.cc
@@ -114,9 +114,17 @@
                           uint32_t &immediate) const
 {
     const CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1);
+    const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
+    const SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
+    const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);

     bool trap_to_sup = false;
     switch (misc_reg) {
+      case MISCREG_DAIF:
+        trap_to_sup = !scr.ns && !scr.eel2 && !sctlr.uma && el == EL0;
+        trap_to_sup = trap_to_sup ||
+            (el == EL0 && (scr.ns || scr.eel2) && !hcr.tge && !sctlr.uma);
+        break;
       case MISCREG_FPCR:
       case MISCREG_FPSR:
       case MISCREG_FPEXC32_EL2:
@@ -127,6 +135,24 @@
             immediate = 0x1E00000;
         }
         break;
+      case MISCREG_DC_CVAU_Xt:
+        trap_to_sup = !sctlr.uci && (!hcr.tge || (!scr.ns && !scr.eel2)) &&
+            el == EL1;
+        break;
+      case MISCREG_CTR_EL0:
+        trap_to_sup = el == EL0 && !sctlr.uct &&
+            (!hcr.tge || (!scr.ns && !scr.eel2));
+        break;
+       case MISCREG_MDCCSR_EL0:
+         {
+             DBGDS32 mdscr = tc->readMiscReg(MISCREG_MDSCR_EL1);
+             trap_to_sup = el == EL0 && mdscr.tdcc &&
+                     (hcr.tge == 0x0 || ( scr.ns == 0x0));
+         }
+         break;
+     case MISCREG_ZCR_EL1:
+        trap_to_sup = el == EL1 && ((cpacr.zen & 0x1) == 0x0);
+        break;
       // Generic Timer
       case MISCREG_CNTFRQ_EL0 ... MISCREG_CNTVOFF_EL2:
         trap_to_sup = el == EL0 &&
diff --git a/src/arch/arm/miscregs_types.hh b/src/arch/arm/miscregs_types.hh
index d3787ff..3578f58 100644
--- a/src/arch/arm/miscregs_types.hh
+++ b/src/arch/arm/miscregs_types.hh
@@ -730,6 +730,7 @@
         Bitfield<14> hde;
         Bitfield<13> res0_;
         Bitfield<12> udccdis;
+        Bitfield<12> tdcc;
         Bitfield<11, 7> res0_2;
         Bitfield<6> err;
         Bitfield<5, 2> moe;

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ief3e0a9f70cc8cd44c1c8215515f36168927362d
Gerrit-Change-Number: 31694
Gerrit-PatchSet: 1
Gerrit-Owner: Jordi Vaquero <jordi.vaqu...@metempsy.com>
Gerrit-MessageType: newchange
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